CY7C67300
Document #: 38-08015 Rev. *J Page 24 of 99
Extended Page n Map Register [R/W]
■Extended Page 1 Map Register 0xC018
■Extended Page 2 Map Register 0xC01A
Register Description
The Extended Page n Map register contains the Page n
high-order address bits. These bits are always appended to
accesses to the Page n Memory mapped space.
Address (Bits [15:0])
The Address field contains the high-order bits 28 to 13 of the
Page n address. The address pins [8:0] (Page n address [21:13])
reflect the content of this register when the CPU accesses the
address 0x8000-0x9FFF. For the SRAM mode, the address pin
on [4:0] (Page n address [17:13]) is used.
Set bit [8] (Page n address [21]) to ‘0’, so that Page n
reads/writes access external areas (SRAM, ROM or periph-
erals). nXMEMSEL is the external chip select for this space.
Upper Address Enable Register [0xC038] [R/W]
Register Description
The Upper Address Enable register enables/disables the four
most significant bits of the external address A[18:15]. This
register defaults to having the Upper Address disabled. Note that
on power up, pins A[18:15] are driven high.
Upper Address Enable (Bit 3)
The Upper Address Enable bit enables/disables the four most
significant bits of the external address A[18:15].
1: Enable A[18:15] of the external memory interface for general
addressing.
0: Disable A[18:15], not available.
Reserved
Write all reserved bits with ’0’.
Table 36. Extended Page n Map Register
Bit # 15 14 13 12 11 10 9 8
Field Address...
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 00000000
Bit # 76543210
Field ...Address
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 00000000
Table 37. External Memory Control Register
Bit # 15 14 13 12 11 10 9 8
Field Reserved
Read/Write --------
Default XXXXXXXX
Bit # 76543210
Field
Reserved Upper
Address
Enable
Reserved
Read/Write - - - - R/W
Default XXXX0XXX
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