Extended Page n Map Register R/W | Cypress CY7C67300 guide

CY7C67300

Extended Page n Map Register [R/W]

■Extended Page 1 Map Register 0xC018

■Extended Page 2 Map Register 0xC01A

Table 36. Extended Page n Map Register

Bit #	15	14	13	12		11	10	9	8
Field					Address...
Read/Write	R/W	R/W	R/W	R/W		R/W	R/W	R/W	R/W
Default	0	0	0	0		0	0	0	0

Bit #	7	6	5	4		3	2	1	0
Field					...Address
Read/Write	R/W	R/W	R/W	R/W		R/W	R/W	R/W	R/W
Default	0	0	0	0		0	0	0	0

Register Description

The Extended Page n Map register contains the Page n high-order address bits. These bits are always appended to accesses to the Page n Memory mapped space.

Address (Bits [15:0])

The Address field contains the high-order bits 28 to 13 of the Page n address. The address pins [8:0] (Page n address [21:13])

Upper Address Enable Register [0xC038] [R/W]

Table 37. External Memory Control Register

reflect the content of this register when the CPU accesses the address 0x8000-0x9FFF. For the SRAM mode, the address pin on [4:0] (Page n address [17:13]) is used.

Set bit [8] (Page n address [21]) to ‘0’, so that Page n reads/writes access external areas (SRAM, ROM or periph- erals). nXMEMSEL is the external chip select for this space.

Bit #	15	14	13	12		11	10	9	8
Field					Reserved
Read/Write	-	-	-	-		-	-	-	-
Default	X	X	X	X		X	X	X	X

Bit #	7	6		5	4	3	2	1	0
			Reserved			Upper		Reserved
Field						Address
Field						Enable
Read/Write	-	-		-	-	R/W
Default	X	X		X	X	0	X	X	X

Register Description

The Upper Address Enable register enables/disables the four most significant bits of the external address A[18:15]. This register defaults to having the Upper Address disabled. Note that on power up, pins A[18:15] are driven high.

Upper Address Enable (Bit 3)

The Upper Address Enable bit enables/disables the four most significant bits of the external address A[18:15].

1:Enable A[18:15] of the external memory interface for general addressing.

0:Disable A[18:15], not available.

Reserved

Write all reserved bits with ’0’.

Document #: 38-08015 Rev. *J

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Cypress CY7C67300 Extended Page n Map Register R/W, Upper Address Enable Register 0xC038 R/W, Upper Address Enable Bit

Contents

EZ-Host Features CY7C67300 Block DiagramTypical Applications Introduction Functional OverviewInterface Descriptions Interface Options for External Memory Bus Pins MEM Pins USB Interface USB Interface Pins Pin Name Pin Number OTG Interface Pins Pin Name Pin NumberOTG Interface External Memory Interface External Memory Interface Pins External Memory Interface Pins Pin Name Pin NumberExternal Memory Interface Block Diagrams Up to 256k x 16 External Code/Data Page Mode General Purpose IO Interface Gpio Uart InterfaceI2C Eeprom Interface Serial Peripheral Interface High-Speed Serial Interface Programmable Pulse/PWM Interface HPI Interface Pins 3 Pin Name Pin Number HPI Interface Pins 3Host Port Interface IDE Interface IDE Throughput Mode IDE Interface Pins Pin Name Pin NumberCharge Pump Interface Pins Pin Name Pin Number Actual Booster Pins Crystal PinsCrystal Pins Pin Name Pin Number Booster Interface Boot Configuration Interface Boot Configuration InterfaceBoot Mode Operational Modes Power Savings and Reset Description Power Saving Mode DescriptionSleep Memory Map Bank Selected 0xC018 0xC01A Document # 38-08015 Rev. *JPage 15 Registers Processor Control Registers Bank Register Bank Register Example Hex Value Binary ValueReserved Revision Register CPU Speed Definition Processor Speed Power Control Register Host/Device 2B Wake Enable BitHost/Device 2A Wake Enable Bit Host/Device 1B Wake Enable Bit Sleep Enable Bit Interrupt Enable Register Halt Enable BitOTG Interrupt Enable Bit SPI Interrupt Enable Bit HSS Interrupt Enable Bit Mailbox Interrupt Enable BitOut Mailbox Interrupt Enable Bit Uart Interrupt Enable Bit USB Diagnostic Register Port 2B Diagnostic Enable BitPort 2A Diagnostic Enable Bit Port 1B Diagnostic Enable Bit External Memory Registers Upper Address Enable Register 0xC038 R/W Upper Address Enable BitExtended Page n Map Register R/W Extended Page n Map Register Timer Registers Watchdog Timer Register Timeout Flag BitLock Enable Bit WDT Enable Bit Timer n Register General USB RegistersUSB n Control Register Port B D+ Status Bit Mode Select Bit Port B Resistors Enable BitPort a Resistors Enable Bit Enable Port a SOF/EOP Enable Bit Reserved Preamble Enable BitUSB Host Only Registers USB Host Only Register Register Name Address Host 1/Host Sync Enable Bit Host n Address Register ISO Enable BitArm Enable Bit Sequence Select Bit Port Select Bit Underflow Flag BitStall Flag Bit NAK Flag Bit Error Flag Bit Sequence Status BitHost n PID Register W Host n PID Register PID Select Definition PID SelectHost n Count Result Register R Host n Count Result Register Endpoint Select Bits Host n Interrupt Enable Register Vbus Interrupt Enable BitID Interrupt Enable Bit Host n Device Address Register SOF/EOP Interrupt Enable Bit Port B Wake Interrupt Enable BitPort a Wake Interrupt Enable Bit Port B Connect Change Interrupt Enable Bit SOF/EOP Interrupt Flag Bit Port B Wake Interrupt Flag BitPort a Wake Interrupt Flag Bit Port B Connect Change Interrupt Flag Bit Host n SOF/EOP Counter Register R Host n SOF/EOP Counter RegisterHost n Frame Register R Host 1 Frame Register 0xC096 Host 2 Frame Register 0xC0B6 IN/OUT Ignore Enable Bit USB Device Only RegistersDevice n Endpoint n Control Register R/W Device n Endpoint n Control Register Stall Enable Bit NAK Interrupt Enable BitEnable Bit Direction Select Bit Device n Endpoint n Count Register R/W Device n Endpoint n Count Register Device n Endpoint n Status Register R/W Device n Endpoint n Status RegisterOUT Exception Flag Bit Exception Flag Bit Setup Flag Bit Sequence Flag BitDevice n Endpoint n Count Result Register R/W Device n Endpoint n Count Result Register Device n Interrupt Enable Register R/W Device n Interrupt Enable Register Port Select BitDevice n Port Select Register R/W Device n Port Select Register SOF/EOP Timeout Interrupt Enable Bit Reset Interrupt Enable BitEP7 Interrupt Enable Bit EP6 Interrupt Enable Bit EP0 Interrupt Enable Bit Device n Address Register WDevice n Address Register Device n Status Register R/W Reset Interrupt Flag Bit EP7 Interrupt Flag BitEP6 Interrupt Flag Bit EP5 Interrupt Flag Bit SOF/EOP Timeout Flag Bit SOF/EOP Timeout Interrupt Counter BitsEP2 Interrupt Flag Bit EP1 Interrupt Flag Bit Vbus Pull-up Enable Bit OTG Control RegistersDevice n SOF/EOP Count Register OTG Control Register Reserved Gpio Registers Write Protect Enable Bit SAS Enable BitMode Select Definition Gpio Configuration 108 HSS Enable Bit Interrupt 0 Enable Bit Interrupt 0 Polarity Select Bit ReservedGpio n Output Data Register Gpio n Input Data Register IDE Registers Mode Select Definition IDE Start Address Register 0xC04A R/WIDE Start Address Register IDE Interrupt Enable Bit IDE Enable BitIDE Stop Address Register IDE Control Register HSS Registers IDE PIO Port Registers 0xC050 0xC06F R/WHSS Registers Register Name Address Xoff Enable Bit CTS Enable BitReceive Interrupt Enable Bit HSS Control Register Packet Mode Select Bit Transmit Ready BitReceive Overflow Flag Bit HSS Baud Rate Register HSS Transmit Gap Register 0xC074 R/W HSS Transmit Gap RegisterTransmit Gap Select Bits HSS Data Register 0xC076 R/W HSS Receive Counter Register 0xC07A R/W HSS Receive Counter Register HSS Transmit Address Register 0xC07C R/W HSS Transmit Address RegisterHSS Transmit Counter Register 0xC07E R/W HSS Transmit Counter Register Vbus to HPI Enable Bit HPI RegistersHPI Breakpoint Register HPI Registers Register Name Address Interrupt Routing Register ID to HPI Enable Bit SOF/EOP2 to HPI Enable BitSOF/EOP2 to CPU Enable Bit SOF/EOP1 to HPI Enable Bit SIEXmsg Register W SIE1msg Register SIE2msg RegisterSIEXmsg Register HPI Mailbox Register 0xC0C6 R/W Reset2 Flag Bit HPI Status PortVbus Flag Bit ID Flag Bit Reset1 Flag Bit SPI RegistersDone1 Flag Bit Mailbox Out Flag Bit 3Wire Enable Bit Phase Select BitMaster Active Enable Bit Master Enable Bit Byte Mode Bit Read Enable BitSPI Control Register SCK Strobe Bit SPI Interrupt Enable Register Transmit Interrupt Enable BitTransfer Interrupt Enable Bit Fifo Error Flag Bit Receive Interrupt Flag Bit Transmit Interrupt Flag BitSPI Interrupt Clear Register Transfer Interrupt Flag Bit CRC Mode Definition CRCMode CRC Polynomial 1514 CRC Enable BitCRC Clear Bit SPI CRC Value Register Receive CRC Bit SPI Data Register 0xC0D6 R/W SPI Data RegisterSPI Transmit Address Register 0xC0D8 R/W SPI Transmit Address Register SPI Transmit Count Register SPI Receive Address RegisterSPI Receive Count Register Uart Registers Uart Status Register 0xC0E2 R Uart Status RegisterReceive buffer full Receive buffer empty Uart Data Register 0xC0E4 R/W PWM Enable Bit PWM RegistersPWM Registers Register Name Address PWM Control Register PWM 3 Enable Bit PWM 2 Enable BitPWM 1 Enable Bit PWM 0 Enable Bit PWM n Start Register R/W PWM n Start RegisterPWM n Stop Register R/W PWM n Stop Register PWM Cycle Count Register 0xC0FA R/W PWM Cycle Count Register Pin Diagram Pin DescriptionsPin Descriptions Name Type D11/MOSI Mosi SPI MosiSCK SPI SCK D8/MISO GPIO29/OTGID GPIO28/TXGPIO27/RX GPIO26/CTS/PWM3 Booster Power input 2.7V to Tie to Gnd for normal operation DC Characteristics Absolute Maximum RatingsOperating Conditions Crystal Requirements XTALIN, Xtalout USB Transceiver GND AC Timing Characteristics Reset TimingClock Timing Sram Read Cycle15 Sram Read Cycle Parameters Description Min Typical Max UnitLOW Sram Write Cycle Sram Write Cycle ParametersParameter Description Min Typical Max Unit High I2C Eeprom Timing-Serial IO SCLSDA OUT HPI Host Port Interface Write Cycle Timing Chip Select Hold Data Access Time, from HPInRD falling HPI Host Port Interface Read Cycle TimingRead Pulse Width Read Cycle Time HSS Byte Mode Transmit HSS Block Mode TransmitHSS Byte and Block Mode Receive IDE Timing Register Summary Hardware CTS/RTS HandshakeRegister Summary HSS SOF/EOP CRC SOF/EOP2 Package Diagrams Ordering InformationOrdering Information Ordering Code Package Type Pb-Free Document History Orig. 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