ARM R4F, r1p3 C15, nVAL Reset Enable Set Register, C15, nVAL Debug Request Enable Set Register

System Control Coprocessor

c15, nVAL Reset Enable Set Register

The nVAL Reset Enable Set Register enables any of the PMC Registers, PMC0-PMC2, and CCNT, to generate a reset request on overflow. If enabled, the reset request is signaled by nVALRESET being asserted LOW.

The nVAL Reset Enable Set Register is:

•A read/write register.

•Always accessible in Privileged mode. The USEREN Register determines access, see c9, User Enable Register on page 6-15.

Figure 4-46shows the bit arrangement for the nVAL Reset Enable Set Register.

31

C

3 2 1 0

Reserved

Cycle count overflow reset request enable P2

Performance monitor counter

overflow reset request enables

P1

P0

Figure 4-46 nVAL Reset Enable Set Register format

Table 4-44shows how the bit values correspond with the nVAL Reset Enable Set Register.

Table 4-44 nVAL Reset Enable Set Register bit functions

Bits	Field	Function
[31]	C	CCNT overflow reset request
[30:3]	Reserved	UNP or SBZP
[2]	P2	PMC2 overflow reset request
[1]	P1	PMC1 overflow reset request
[0]	P0	PMC0 overflow reset request

To access the nVAL Reset Enable Set Register, read or write CP15 with:

MRC p15, 0, <Rd>, c15, c1, 2 ; Read nVAL Reset Enable Set Register MCR p15, 0, <Rd>, c15, c1, 2 ; Write nVAL Reset Enable Set Register

On reads, this register returns the current setting. On writes, reset requests can be enabled. If a reset request has been enabled, it is disabled by writing to the nVAL Reset Enable Clear Register. See c15, nVAL Reset Enable Clear Register on page 4-67.

If one or more of the reset request fields (P2, P1, P0, and C) is enabled, and the corresponding counter overflows, then a reset request is indicated by nVALRESET being asserted LOW. This signal can be passed to a system reset controller.

c15, nVAL Debug Request Enable Set Register

The Debug Request Enable Set Register enables any of the PMC Registers, PMC0-PMC2, and CCNT, to generate a debug request on overflow. If enabled, the debug request is signaled by VALEDBGRQ being asserted HIGH.

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