ARM r1p3, R4F manual Aborts, Prefetch aborts, Data aborts, Precise aborts

Programmer’s Model

2.8.4Aborts

When the processor's memory system cannot complete a memory access successfully, an abort is generated. Aborts can occur for a number of reasons, for example:

•a permission fault indicated by the MPU

•an error response to a transaction on the AXI memory bus

•an error detected in the data by the ECC checking logic.

An error occurring on an instruction fetch generates a prefetch abort. Errors occurring on data accesses generate data aborts. Aborts are also categorized as being either precise or imprecise.

When a prefetch or data abort occurs, the processor takes the appropriate type of exception. See Exception entry and exit summary on page 2-16for more information. Additional information about the type of abort is stored in registers, and signaled as events. See Fault handling on page 8-7for more details of the types of fault that can cause an abort and the information that the processor provides about these faults.

Prefetch aborts

When a Prefetch Abort (PABT) occurs, the processor marks the prefetched instruction as invalid, but does not take the exception until the instruction is to be executed. If the instruction is not executed, for example because a branch occurs while it is in the pipeline, the abort does not take place.

All prefetch aborts are precise.

Data aborts

An error occurring on a data memory access can generate a data abort. If the instruction generating the memory access is not executed, for example, because it fails its condition codes, or is interrupted, the data abort does not take place.

A Data Abort (DABT) can be either precise or imprecise, depending on the type of fault that caused it.

The processor implements the base restored Data Abort model, as opposed to a base updated Data Abort model.

With the base restored Data Abort model, when a Data Abort exception occurs during the execution of a memory access instruction, the processor hardware always restores the base register to the value it contained before the instruction was executed. This removes the requirement for the Data Abort handler to unwind any base register update that the aborted instruction might have specified. This simplifies the software Data Abort handler. For more information, see the ARM Architecture Reference Manual.

Precise aborts

A precise abort, also known as a synchronous abort, is one for which the exception is guaranteed to be taken on the instruction that generated the aborting memory access. The abort handler can use the value in the Link Register (r14_abt) to determine which instruction generated the abort, and the value in the Saved Program Status Register (SPSR_abt) to determine the state of the processor when the abort occurred.

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