Cycle Timings and Interlock Behavior

14.10 Processor state updating instructions

This section describes the cycle timing behavior for the MSR, MRS, CPS, and SETEND instructions. Table 14-11shows processor state updating instructions and their cycle timing behavior.

Table 14-11 Processor state updating instructions cycle timing behavior

Instruction

Cycles

Comments

 

 

 

MRS

1

All MRS instructions

 

 

 

MSR

5

All other MSR instructions to the CPSR

 

 

 

MSR SPSR

1

All MSR instructions to the SPSR

 

 

 

CPS <effect> <iflags>

1

Interrupt masks only

 

 

 

CPS <effect> <iflags>, #<mode>

1

Mode changing

 

 

 

SETEND

1

-

 

 

 

ARM DDI 0363E

Copyright © 2009 ARM Limited. All rights reserved.

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ARM r1p3, R4F Processor state updating instructions, All MRS instructions, All MSR instructions to the Spsr, Mode changing