ARM r1p3, R4F manual About the MPU, Default memory map, True

Memory Protection Unit

7.1About the MPU

The MPU works with the L1 memory system to control accesses to and from L1 and external memory. For a full architectural description of the MPU, see the ARM Architecture Reference Manual.

The MPU enables you to partition memory into regions and set individual protection attributes for each region. The MPU supports zero, eight, or twelve memory regions.

Note

If the MPU has zero regions, you cannot enable or program the MPU. Attributes are only determined from the default memory map when zero regions are implemented.

Each region is programmed with a base address and size, and the regions can be overlapped to enable efficient programming of the memory map. To support overlapping, the regions are assigned priorities, with region 0 having the lowest priority and region 11 having the highest. The MPU returns access permissions and attributes for the highest priority region where the address hits.

The MPU is programmed using CP15 registers c1 and c6, see MPU control and configuration on page 4-5.Memory region control read and write access is permitted only from Privileged modes.

Table 7-1shows the default memory map.

				Table 7-1 Default memory map
Address	Instruction memory type		Data memory type
					Execute Never
range	Instruction	Instruction	Data cache	Data cache
	cache enabled	cache disabled	enabled	disabled
0xFFFFFFFF	Normal	Normal	Strongly Ordered	Strongly	Instruction
	Non-cacheable	Non-cacheable		Ordered	execution only
0xF0000000
	only if HIVECS is	only if HIVECS is			permitted if
	TRUE	TRUE			HIVECS is TRUE
0xEFFFFFFF	-	-	Strongly Ordered	Strongly	Execute Never
				Ordered
0xC0000000
0xBFFFFFFF	-	-	Shared Device	Shared	Execute Never
				Device
0xA0000000
0x9FFFFFFF	-	-	Non-shared	Non-shared	Execute Never
			Device	Device
0x80000000
0x7FFFFFFF	Normal,	Normal,	Normal,	Normal,	Instruction
	Cacheable,	Non-cacheable,	Non-cacheable,	Non-cacheable,	execution permitted
0x60000000
	Non-shared	Non-shared	Shared	Shared
0x5FFFFFF	Normal,	Normal,	Normal,	Normal,	Instruction
	Cacheable,	Non-cacheable,	WT Cacheable,	Non-cacheable,	execution permitted
0x40000000
	Non-shared	Non-shared	Non-shared	Shared
0x3FFFFFFF	Normal,	Normal,	Normal,	Normal,	Instruction
	Cacheable,	Non-cacheable,	WBWA Cacheable	Non-cacheable,	execution permitted
0x00000000
	Non-shared	Non-shared	, Non-shared	Shared

ARM DDI 0363E	Copyright © 2009 ARM Limited. All rights reserved.	7-2
ID013010	Non-Confidential, Unrestricted Access