ARM r1p3, R4F manual Store buffer merging, Store buffer behavior, Store buffer draining

Level One Memory System

Store buffer merging

The store buffer has merging capabilities. If a previous write access has updated an entry, other write accesses on the same line can merge into this entry. Merging is only possible for stores to Normal memory.

Merging is possible between several entries that can be linked together if the data inside the different entries belong to the same cache line.

No merging occurs for writes to Strongly Ordered or Device memory. The processor automatically drains the store buffer before performing Strongly Ordered accesses or Device reads.

Store buffer behavior

The store buffer redirects write requests to the following blocks:

•Cache controller for Cacheable write hits:

The store buffer sends a cache lookup to check that the cache hits in the specified line, and if so, the store buffer merges its data into the cache when the entry is drained.

•AXI master interface:

—For Non-cacheable stores or write-through Cacheable stores, a write access is performed on the AXI master interface.

—For write-back, write-allocate stores that miss in the data cache, a linefill is started using either of the two linefill buffers. When the linefill data is returned from the L2 memory system, the data in the store buffer is merged into the linefill buffer.

Store buffer draining

A store buffer entry is drained if:

•All bytes in the entry have been written. This might result from merging.

•The entry can be merged into a linefill buffer.

•The entry contains a store to Device or Strongly Ordered memory.

The store buffer is completely drained when:

•an explicit drain request is done for:

—system control coprocessor cache maintenance operations

—a DMB or DSB instruction

—a load or store to Strongly Ordered memory

—an exclusive load or store to Shared memory

—a SWP or SWPB to Non-cacheable memory.

•the store buffer is full or likely to become full.

The store buffer is drained of all stores to Device memory before a load is performed from

Device memory.

8.5.2Cache maintenance operations

All cache maintenance operations are done through the system control coprocessor, CP15. The system control coprocessor operations supported for the data cache are:

•Invalidate all

•Invalidate by address (MVA)

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