ARM r1p3, R4F manual MPU control and configuration, Cache control and configuration

System Control Coprocessor

4.1.3MPU control and configuration

The MPU control and configuration registers:

•control program access to memory

•designate areas of memory as either:

—Normal, Non-cacheable

—Normal, Cacheable

—Device

—Strongly Ordered.

•detect MPU faults and external aborts.

The MPU control and configuration registers consist of one read-only register and eleven read/write registers. Figure 4-2shows the arrangement of registers in this functional group.

CRn	Opcode_1			CRm			Opcode_2
c0										MPU Type Register
			0		c0			4
c5										Data Fault Status Register
			0		c0				0
										Instruction Fault Status Register
								1
										Auxilary Data Fault Status Register
					c1			0
										Auxilary Instruction Fault Status Register
								1
c6										Data Fault Address Register
			0		c0			0
								2		Instruction Fault Address Register
										Region Base Register
					c1			0
										Region Size and Enable Register
								2
										Region Access Control Register
								4
										Memory Region Number Register
					c2			0
c15										Correctable Fault Location Register
			0		c3			0
		Read-only				Read/write				Write-only	Accessible in User mode

Figure 4-2 MPU control and configuration registers

MPU control and configuration can behave:

•as a set of numbers, with values that describe aspects of the MPU or indicate its current state

•as a set of operations that act on the MPU.

4.1.4Cache control and configuration

The cache control and configuration registers:

•provide information on the size and architecture of the instruction and data caches

•control cache maintenance operations that include clean and invalidate caches, drain and flush buffers, and address translation

•override cache behavior during debug or interruptible cache operations.

The cache control and configuration registers consist of three read-only registers, one read/write register, and a number of write-only registers. Figure 4-3 on page 4-6shows the arrangement of the registers in this functional group.

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