ARM r1p3, R4F manual Example interlocks 14-11

		List of Tables
Table 14-5	QADD, QDADD, QSUB, and QDSUB instruction cycle timing behavior	14-9
Table 14-6	Media data-processing instructions cycle timing behavior	14-10
Table 14-7	Sum of absolute differences instruction timing behavior	14-11
Table 14-8	Example interlocks	14-11
Table 14-9	Example multiply instruction cycle timing behavior	14-12
Table 14-10	Branch instruction cycle timing behavior	14-15
Table 14-11	Processor state updating instructions cycle timing behavior	14-16
Table 14-12	Cycle timing behavior for stores and loads, other than loads to the PC	14-17
Table 14-13	Cycle timing behavior for loads to the PC	14-17
Table 14-14	<addr_md_1cycle> and <addr_md_3cycle> LDR example instruction explanation	14-18
Table 14-15	Load and Store Double instructions cycle timing behavior	14-20
Table 14-16	<addr_md_1cycle> and <addr_md_3cycle> LDRD example instruction explanation	14-20
Table 14-17	Cycle timing behavior of Load and Store Multiples, other than load multiples including the PC
	14-21
Table 14-18	Cycle timing behavior of Load Multiples, with PC in the register list (64-bit aligned)	14-22
Table 14-19	RFE and SRS instructions cycle timing behavior	14-24
Table 14-20	Synchronization instructions cycle timing behavior	14-25
Table 14-21	Coprocessor instructions cycle timing behavior	14-26
Table 14-22	SVC, BKPT, Undefined, prefetch aborted instructions cycle timing behavior	14-27
Table 14-23	IT and NOP instructions cycle timing behavior	14-28
Table 14-24	Floating-point register transfer instructions cycle timing behavior	14-29
Table 14-25	Floating-point load/store instructions cycle timing behavior	14-30
Table 14-26	Floating-pointsingle-precision data processing instructions cycle timing behavior	14-32
Table 14-27	Floating-pointdouble-precision data processing instructions cycle timing behavior	14-33
Table 14-28	Permitted instruction combinations	14-35
Table 15-1	Miscellaneous input ports timing parameters:	15-3
Table 15-2	Configuration input port timing parameters	15-3
Table 15-3	Interrupt input ports timing parameters	15-4
Table 15-4	AXI master input port timing parameters	15-4
Table 15-5	AXI slave input port timing parameters	15-5
Table 15-6	Debug input ports timing parameters	15-6
Table 15-7	ETM input ports timing parameters	15-6
Table 15-8	Test input ports timing parameters	15-7
Table 15-9	TCM interface input ports timing parameters	15-7
Table 15-10	Miscellaneous output port timing parameter	15-8
Table 15-11	Interrupt output ports timing parameters	15-8
Table 15-12	AXI master output port timing parameters	15-8
Table 15-13	AXI slave output ports timing parameters	15-9
Table 15-14	Debug interface output ports timing parameters	15-10
Table 15-15	ETM interface output ports timing parameters	15-11
Table 15-16	Test output ports timing parameters	15-11
Table 15-17	TCM interface output ports timing parameters	15-11
Table 15-18	FPU output port timing parameters	15-12
Table A-1	Global signals	A-3
Table A-2	Configuration signals	A-4
Table A-3	Interrupt signals	A-7
Table A-4	AXI master port signals for the L2 interface	A-8
Table A-5	AXI master port error detection signals	A-10
Table A-6	AXI slave port signals for the L2 interface	A-10
Table A-7	AXI slave port error detection signals	A-12
Table A-8	ATCM port signals	A-13
Table A-9	B0TCM port signals	A-13
Table A-10	B1TCM port signals	A-14
Table A-11	Dual core interface signals	A-16
Table A-12	Debug interface signals	A-17
Table A-13	Debug miscellaneous signals	A-17
Table A-14	ETM interface signals	A-19
Table A-15	Test signals	A-20
Table A-16	MBIST signals	A-21
Table A-17	Validation signals	A-22

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