Debug

Note

The CP14 debug instructions are defined as having Opcode_1 set to 0.

 

 

Table 11-2 CP14 debug registers summary

 

 

 

Instruction

Mnemonic

Description

 

 

 

MRC p14, 0, <Rd>, c0, c0, 0

DIDR

Debug Identification Register. See CP14 c0, Debug ID Register on

 

 

page 11-10.

 

 

 

MRC p14, 0, <Rd>, c1, c0, 0

DRAR

Debug ROM Address Register. See CP14 c0, Debug ROM Address

 

 

Register on page 11-12.

 

 

 

MRC p14, 0, <Rd>, c2, c0, 0

DSAR

Debug Self Address Register. See CP14 c0, Debug Self Address

 

 

Offset Register on page 11-12.

 

 

 

MRC p14, 0, <Rd>, c0, c5, 0

DTRRX

Host to Target Data Transfer Register. See Data Transfer Register on

STC p14, c5, <addressing mode>

 

page 11-18.

 

 

 

MCR p14, 0, <Rd>, c0, c5, 0

DTRTX

Target to Host Data Transfer Register. See Data Transfer Register on

LDC p14, c5, <addressing mode>

 

page 11-18.

 

 

 

MRC p14, 0, <Rd>, c0, c1, 0

DSCR

Debug Status and Control Register. See CP14 c1, Debug Status and

MRC p14, 0, PC, c0, c1, 0

 

Control Register on page 11-14.

 

 

 

11.3.4Memory-mapped registers

Table 11-3shows the complete list of memory-mapped registers accessible at the APB slave interface.

Note

You must ensure that the base address of this 4KB register map is aligned to a 4KB boundary in physical memory.

 

 

 

 

 

Table 11-3 Debug memory-mapped registers

 

 

 

 

 

 

 

 

Offset

Register

Access

Mnemonic

Description

 

 

(hex)

number

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x000

c0

R

DIDR

CP14 c0, Debug ID Register on page 11-10

 

 

 

 

 

 

 

 

 

0x004-0x014

c1-c5

R

-

RAZ

 

 

 

 

 

 

 

 

 

0x18

c6

RW

WFAR

Watchpoint Fault Address Register on page 11-19

 

 

 

 

 

 

 

 

 

0x01C

c7

RW

VCR

Vector Catch Register on page 11-19

 

 

 

 

 

 

 

 

 

0x020

c8

R

-

RAZ

 

 

 

 

 

 

 

 

 

0x024

c9

RW

ECR

Not implemented in this processor. Reads as zero.

 

 

 

 

 

 

 

 

 

0x028

c10

RW

DSCCR

Debug State Cache Control Register on page 11-21.

 

 

 

 

 

 

 

 

 

0x02C

c11

R

-

RAZ

 

 

 

 

 

 

 

 

 

0x030-0x07C

c12-c31

R

-

RAZ

 

 

 

 

 

 

ARM DDI 0363E

 

Copyright © 2009 ARM Limited. All rights reserved.

11-6

ID013010

 

Non-Confidential, Unrestricted Access

 

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ARM r1p3, R4F manual Memory-mapped registers, Instruction Mnemonic Description, Debug memory-mapped registers