ARM r1p3, R4, R4F

Level One Memory System

ID013010 Non-Confidential, Unrestricted Access

Any detected error is signaled with the appropriate event.

Clean data cache by set/way

This operation does not require a cache lookup. It refers to a particular cache line.

The tag and dirty RAMs for the cache line are checked.

Note

When force write-through is enabled, the dirty bit is ignored.

If the tag or dirty RAM has an uncorrectable error, the data is not written to memory.

If the line is dirty, the data is written back to external memory. If the data has an uncorrectable

error, the words with the error have their WSTRBM AXI signal deasserted. If there is a

correctable error, the line has the error corrected inline before it is written back to memory.

Any uncorrectable errors found cause an imprecise abort. An imprecise abort can also be raised

on a correctable error if aborts on RAM errors are enabled in the Auxiliary Control Register.

Any detected error is signaled with the appropriate event.

Clean and invalidate data cache by address

This operation requires a cache lookup. Any correctable errors found in the set that was looked

up are fixed and, if the address in question is found in the set, the instruction carries on with the

clean and invalidate operation. When the tag lookup is done, the dirty RAM is checked.

Note

When force write-through is enabled, the dirty bit is ignored.

If the tag or dirty RAM has an uncorrectable error, the data is not written to memory.

If the line is dirty, the data is written back to external memory. If the data has an uncorrectable

error, the words with the error have their WSTRBM AXI signal deasserted. If there is a

correctable error, the line has the error corrected inline before it is written back to memory.

Any uncorrectable errors found cause an imprecise abort. An imprecise abort can also be raised

on a correctable error if aborts on RAM errors are enabled in the Auxiliary Control Register.

Any detected error is signaled with the appropriate event.

Clean and invalidate data cache by set/way

This operation does not require a cache lookup. It refers to a particular cache line.

The tag and dirty RAMs for the cache line are checked.

Note

When force write-through is enabled, the dirty bit is ignored.

If the tag or dirty RAM has an uncorrectable error, the data is not written to memory.

If the line is dirty, the data is written back to external memory. If the data has an uncorrectable

error, the words with the error have their WSTRBM AXI signal deasserted. If there is a

correctable error, the line has the error corrected inline before it is written back to memory.