ARM R4F, r1p3 An instruction that is architecturally Undefined, By individual implementations

Glossary

Illegal instruction	An instruction that is architecturally Undefined.
Implementation-defined	Means that the behavior is not architecturally defined, but should be defined and documented
	by individual implementations.
Implementation-specific	Means that the behavior is not architecturally defined, and does not have to be documented by
	individual implementations. Used when there are a number of implementation options available
	and the option chosen does not affect software compatibility.
Infinity	In the IEEE 754 standard format to represent infinity, the exponent is the maximum for the
	precision and the fraction is all zeros.
Input exception	An exception condition in which one or more of the operands for a given operation are not
	supported by the hardware. The operation bounces to support code for processing.
Instruction cache	A block of on-chip fast access memory locations, situated between the processor and main
	memory, used for storing and retrieving copies of often used instructions. This is done to greatly
	increase the average speed of memory accesses and so improve processor performance.
Instruction Synchronization Barrier (ISB)
	An operation to ensure that the prefetch buffer is flushed of all out-of-date instructions.
Intermediate result	An internal format used to store the result of a calculation before rounding. This format can have
	a larger exponent field and fraction field than the destination format.
Interrupt handler	A program to which control of the processor is passed when an interrupt occurs.
Interrupt vector	One of a number of fixed addresses in low memory, or in high memory if high vectors are
	configured, that contains the first instruction of the corresponding interrupt handler.
Invalidate	To mark a cache line as being not valid by clearing the valid bit. This must be done whenever
	the line does not contain a valid cache entry. For example, after a cache flush all lines are invalid.
ISB	See Instruction Synchronization Barrier.
LE	Little endian view of memory in both byte-invariant and word-invariant systems. See also
	Byte-invariant, Word-invariant.
Line	See Cache line.
Little-endian	Byte ordering scheme in which bytes of increasing significance in a data word are stored at
	increasing addresses in memory.
	See also Big-endian and Endianness.
Little-endian memory	Memory in which:
	•	a byte or halfword at a word-aligned address is the least significant byte or halfword
		within the word at that address
	•	a byte at a halfword-aligned address is the least significant byte within the halfword at that

address.

See also Big-endian memory.

Load/store architecture

A processor architecture where data-processing operations only operate on register contents, not directly on memory contents.

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