ARM r1p3, R4, R4F

Level One Memory System

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• Invalidate by Set/Way combination

• Clean by address (MVA)

• Clean by Set/Way combination

• Clean and Invalidate by address (MVA)

• Clean and Invalidate by Set/Way combination

•Data Memory Barrier (DMB) and Data Synchronization Barrier (DSB) operations.

The system control coprocessor operations supported for the instruction cache are:

• Invalidate all

• Invalidate by address.

For more information on cache operations, see Cache operations on page 4-54.

8.5.3 Cache error detection and correction

This section describes how the processor detects, handles, reports, and corrects cache memory

errors. Memory errors have Fault Status Register (FSR) values to distinguish them from other

abort causes.

This section describes:

•Error build options

•Address decoder faults on page8-21

•Handling cache parity errors on page 8-21

•Handling cache ECC errors on page8-22

•Errors on instruction cache read on page8-23

•Errors on data cache read on page8-23

•Errors on data cache write on page8-23

•Errors on evictions on page8-23

•Errors on cache maintenance operations on page8-23.

Error build options

The caches can detect and correct errors depending on the build options used in the

implementation. The build options for the instruction cache can be different to the data cache.

If the parity build option is enabled, the cache is protected by parity bits. For both the instruction

and data cache, the data RAMs include one parity bit per byte of data. The tag RAM contains

one parity bit to cover the tag and valid bit.

If the ECC build option is enabled:

• The instruction cache is protected by a 64-bit ECC scheme. The data RAMs include eight

bits of ECC code for every 64 bits of data. The tag RAMs include seven bits of ECC code

to cover the tag and valid bit.

• The data cache is protected by a 32-bit ECC scheme. The data RAMs include seven bits

of ECC code for every 32 bits of data. The tag RAMs include seven bits of ECC code to

cover the tag and valid bit. The dirty RAM includes four bits of ECC to cover the dirty bit

and the two outer attributes bits.