ARM R4F, r1p3 manual Branches, Branch instruction cycle timing behavior

Cycle Timings and Interlock Behavior

14.9Branches

This section describes the cycle timing behavior for the B, BL, BLX, BX, BXJ, CBNZ, CBZ, TBB, and TBH instructions. Branches are subject to dynamic and return stack predictions. Table 14-10shows example branch instructions and their cycle timing behavior.

			Table 14-10 Branch instruction cycle timing behavior
Example instruction	Cycles	Memory	Comments
		cycles
B<label>, BL<label>a,	1	-	Correct dynamic prediction
BLX<label>a
	8	-	Incorrect dynamic prediction
BX <Rm>b	1	-	Correct return stack prediction
	9	-	Incorrect return stack prediction
BX <cond> <Rm>b	1	-	Correct condition prediction and correct return stack prediction
	8	-	Incorrect condition prediction
	9	-	Correct condition prediction and incorrect return stack prediction
BXJ <cond> <Rm>	1	-	Condition code fails
	9	-	Condition code passes
BLX <Rm>	9	-	-
BLX <cond> <Rm>	1	-	Condition code fails
	9	-	Condition code passes
CBZ <Rn>, <label>, CBNZ	1	-	Correct condition prediction
<Rn>, <label>
	8	-	Incorrectly predicted
TBB [<Rn>, <Rm>]c	9	1	Condition code fails
	9	1	Condition code passes
TBH [<Rn>, <Rm>, LSL#1]c	9	1	Condition code fails
	9	1	Condition code passes

a.Return stack push.

b.Return stack pop, if condition passes.

c.<Rn> and <Rm> are Very Early Regs.

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