ARM R4F, r1p3 manual Data format, instruction cache, with ECC

			Level Two Interface
Table 9-33 Data format, instruction cache and data cache, with parity
		Data bit	Description
	[63:50]		Not used, read-as-zero
	[49]		Parity bit for data value [31:24] or [63:56]
	[48]		Parity bit for data value [23:16] or [55:48]
	[47:32]		Data value, [31:16] or [63:48]
	[31:18]		Not used, read-as-zero
	[17]		Parity bit for data value [15:8] or [47:40]
	[16]		Parity bit for data value [7:0] or [39:32]
	[15:0]		Data value, [15:0] or [47:32]
	Table 9-34 Data format, instruction cache, with ECC
Data bit	Description
[63:52]	Not used, read-as-zero
[51:48]	Upper or lower half of the ECC 64 codea
[47:32]	Data value, [31:16] or [63:48]
[31:20]	Not used, read-as-zero
[19:16]	Upper or lower half of the ECC 64 codeb
[15:0]	Data value, [15:0] or [47:32]

a.If accessing bits [31:16] of the data, bits [51:48] hold the lower half of the ECC code. If accessing bits [63:48] of the data, bits [51:48] hold the upper half of the ECC code.

b.If accessing bits [15:0] of the data, bits [19:16] hold the lower half of the ECC code. If accessing bits [47:32] of the data, bits [19:16] hold the upper half of the ECC code.

Table 9-35 Data format, data cache, with ECC

Data bit	Description
[63:55]	Not used, read-as-zero
[54:48]	ECC 32 codea
[47:32]	Data value, [31:16] or [63:48]
[31:23]	Not used, read-as-zero
[22:16]	ECC 32 code
[15:0]	Data value [15:0] or [47:32]

a.For a 64 bit access, the ECC bits are duplicated in bits [22:16] and bits [54:48], and the two copies are identical. For a 32 bit access, the ECC bits refer to the whole 32 bit data value, even though only 16 bits of data are accessed.

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