ARM r1p3, R4, R4F

System Control Coprocessor

ID013010 Non-Confidential, Unrestricted Access

The Data Fault Status Register is:

• a read/write register

• accessible in Privileged mode only.

Figure 4-31 shows the bit arrangement in the Data Fault Status Register.

Figure 4-31 Data Fault Status Register format

Table4-28 shows how the bit values correspond with the Data Fault Status Register functions.

To use the DFSR read or write CP15 with:

MRC p15, 0, <Rd>, c5, c0, 0 ; Read Data Fault Status Register

MCR p15, 0, <Rd>, c5, c0, 0 ; Write Data Fault Status Register

c5, Instruction Fault Status Register

The Instruction Fault Status Register (IFSR) holds status information regarding the source of

the last instruction abort.

The Instruction Fault Status Register is:

• a read/write register

• accessible in Privileged mode only.

Figure 4-32 on page 4-47 shows the bit arrangement in the Instruction Fault Status Register.

Domain

Reserved

31 8 7 4 3 0

Status

10111213

Table4-28 Data Fault Status Register bit functions

Bits Field Function

[31:13] Reserved SBZ.

[12] SD Distinguishes between an AXI Decode or Slave error on an external abort. This bit is only valid

for external aborts. For all other aborts types of abort, this bit is set to zero:

0 = AXI Decode error (DECERR) caused the abort

1 = AXI Slave error (SLVERR, or OKAY in response to exclusive read transaction) caused the

abort.

[11] RW Indicates whether a read or write access caused an abort:

0 = read access caused the abort

1 = write access caused the abort.

[10]aS Part of the Status field.

[9:8] - Always read as 0. Writes ignored.

[7:4] Domain SBZ. This is because domains are not implemented in this processor.

[3:0]aStatus Indicates the type of fault generated. To determine the data fault, you must use bit [12] and bit [10]

in conjunction with bits [3:0].

a. For more information on how these bits are used in reporting faults, see Table4-27 on page 4-45.