ARM r1p3, R4, R4F 12.3 System registers

FPU Programmer’s Model

ID013010 Non-Confidential, Unrestricted Access

12.3 System registers

The VFPv3 architecture describes the following system registers:

•Floating-Point System ID Register, FPSID on page12-5

•Floating-Point Status and Control Register, FPSCR on page12-6

•Floating-Point Exception Register, FPEXC on page12-7

•Media and VFP Feature Registers, MVFR0 and MVFR1 on page12-8.

Table12-1 shows the VFP system registers in the Cortex-R4F FPU.

Note

The FPSID, MVFR0, and MVFR1 Registers are read-only. Attempts to write these registers are

ignored.

Table12-2 shows that some of the VFP system registers can only be accessed in Privileged

modes.

Table12-2 shows that a Privileged mode is sometimes required to access a VFP system register.

When a Privileged mode is required, an instruction that attempts to access a register in a

nonprivileged mode takes the Undefined Instruction exception.

For a VFP system register to be accessible, it must follow the rules in Table12-2 and the VFP

must also be accessible according to the Coprocessor Access Register. See c1, Coprocessor

Access Register on page 4-44 for more information.

Table12-1 VFP system registers

Floating-Point System ID Register, FPSID b0000 Read-only

0x4102314x

Floating-Point Status and Control Register, FPSCR b0001 Read/write

0x00000000

Floating-Point Exception Register, FPEXC b1000 Read/write

0x00000000

VFP Feature Register 0, MVFR0 b0111 Read-only

0x10110221

VFP Feature Register 1, MVFR1 b0110 Read-only

0x00000001

a. Bits [3:0] of the FPSID depend on the product revision. See the FPSID register description for more information.

Table12-2 Accessing VFP system registers

Privileged access User access

FPEXC EN=0 FPEXC EN=1 FPEXC EN=0 FPEXC EN=1

FPSID Permitted Permitted Not permitted Not permitted

FPSCR Not permitted Permitted Not permitted Permitted

MVFR0, MVFR1 Permitted Permitted Not permitted Not permitted

FPEXC Permitted Permitted Not permitted Not permitted