ARM R4F Increment of +2, See Debug test access port, Destination precision, See Unpredictable

	Glossary
Stride	The stride field, FPSCR[21:20], specifies the increment applied to register addresses in short
	vector operations. A stride of 00, specifying an increment of +1, causes a short vector operation
	to increment each vector register by +1 for each iteration, while a stride of 11 specifies an
	increment of +2.
Subnormal value	A value in the range (–2Emin< x < 2Emin), except for 0. In the IEEE 754 standard format for
	single-precision and double-precision operands, a subnormal value has a zero exponent and a
	nonzero fraction field. The IEEE 754 standard requires that the generation and manipulation of
	subnormal operands be performed with the same precision as normal operands.
Support code	Software that must be used to complement the hardware to provide compatibility with the IEEE
	754 standard. The support code has a library of routines that performs supported functions, such
	as divide with unsupported inputs or inputs that might generate an exception, and as well as
	operations beyond the scope of the hardware. The support code has a set of exception handlers
	to process exceptional conditions in compliance with the IEEE 754 standard.
Synchronization primitive	The memory synchronization primitive instructions are those instructions that are used to ensure
	memory synchronization. That is, the LDREX, STREX, SWP, and SWPB instructions.
Tag	The upper portion of a block address used to identify a cache line within a cache. The block
	address from the CPU is compared with each tag in a set in parallel to determine if the
	corresponding line is in the cache. If it is, it is said to be a cache hit and the line can be fetched
	from cache. If the block address does not correspond to any of the tags, it is said to be a cache
	miss and the line must be fetched from the next level of memory.
	See also Cache terminology diagram on the last page of this glossary.
TAP	See Debug test access port.
Thumb state	A processor that is executing Thumb (16-bit and 32-bit) instructions is operating in Thumb
	state.

Tightly coupled memory (TCM)

An area of low latency memory that provides predictable instruction execution or data load timing in cases where deterministic performance is required. TCMs are suited to holding:

	•	critical routines (such as for interrupt handling)
	•	scratchpad data
	•	data types whose locality is not suited to caching
	•	critical data structures (such as interrupt stacks).
Tiny	A nonzero result or value that is between the positive and negative minimum normal values for
	the destination precision.
Trace port	A port on a device, such as a processor or ASIC, used to output trace information.
Trap	A exceptional condition that has the respective exception enable bit set in the FPSCR register.
	The user trap handler is executed.
Unaligned	A data item stored at an address that is not divisible by the number of bytes that defines the data
	size is said to be unaligned. For example, a word stored at an address that is not divisible by four.
Undefined	Indicates an instruction that generates an Undefined instruction trap. See the ARM Architecture
	Reference Manual for more information on ARM exceptions.
UNP	See Unpredictable.
Unpredictable	The result of an instruction or control register field value that cannot be relied upon.
	Unpredictable instructions or results must not represent security holes, or halt or hang the
	processor, or any parts of the system.

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