ARM r1p3, R4F manual Device Power-down and Reset Control Register, Prcr functions, Systems

Debug

a.Cortex-R4 does not implement the Security Extensions, so all the debug features are considered secure.

11.4.18Device Power-down and Reset Control Register

The PRCR is a read/write register that controls reset and power-down related functionality.

Figure 11-14shows the bit arrangement of the PRCR.

31 3 2 1 0

Reserved

Hold internal reset

Force internal reset

No Power-down

Figure 11-14 PRCR format

Table 11-23shows how the bit values correspond with the Device Power down and Reset

Control Register functions.

			Table 11-23 PRCR functions
Bits	Field	Function
[31:3]	Reserved	Do not modify on writes. On reads, the value returns zero.
[2]	Hold internal	Hold internal reset bit. This bit can be used to prevent the processor from running again before
	reset	the debugger detects a power-down event and restores the state of the debug registers in the
		processor. This bit does not have any effect on initial system power-up as nSYSPORESET
		clears it.
		0	= Do not hold internal reset on power-up or warm reset. This is the reset value.
		1	= Hold the processor non-debug logic in reset on warm reset until this flag is cleared.
[1]	Force	When a 1 is written to this bit, the processor asserts the DBGRSTREQ output for four cycles.
	internal reset	You can connect this output to an external reset controller which, in turn, resets the processor.
[0]	No	When set to 1, the DBGNOPWRDWN output signal is HIGH. This output connects to the
	power-down	system power controller and is interpreted as a request to operate in emulate mode. In this mode,
		the processor is not actually powered down when requested by software or hardware
		handshakes. This mode is useful when debugging applications on top of working operating
		systems.
		0	= DBGNOPWRDWN is LOW. This is the reset value
		1	= DBGNOPWRDWN is HIGH.

11.4.19 Device Power-down and Reset Status Register

The PRSR is a read-only register that provides information about the reset and power-down state of the processor.

Figure 11-15 on page 11-31shows the bit arrangement of the PRSR.

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