ARM r1p3, R4F manual Data processing instructions, Cycle counts if destination is not PC

Cycle Timings and Interlock Behavior

14.3Data processing instructions

This section describes the cycle timing behavior for the ADC, ADD, ADDW, AND, ASR, BIC, CLZ, CMN, CMP,

EOR, LSL, LSR, MOV, MOVT, MOVW, MVN, ORN, ORR, ROR, RRX, RSB, RSC, SBC, SUB, SUBW, TEQ, and TST instructions.

This section describes:

•Cycle counts if destination is not PC

•Cycle counts if destination is the PC

•Example interlocks on page 14-8

14.3.1Cycle counts if destination is not PC

Table 14-3shows the cycle timing behavior for data processing instructions if their destination is not the PC. You can substitute ADD with any of the data processing instructions identified in the opening paragraph of this section.

Table 14-3 Data Processing Instruction cycle timing behavior if destination is not PC

Example instruction	Cycles	Early	Late	Result	Comments
		Reg	Reg	latency
ADD <Rd>, <Rn>, #<immed>	1	-	-	1	Normal cases.
ADD <Rd>, <Rn>, <Rm>	1	-	-	1
ADD <Rd>, <Rn>, <Rm>, LSL #<immed>	1	<Rm>	-	1	Requires a shifted source register.
ADD <Rd>, <Rn>, <Rm>, LSL <Rs>	1	<Rm>, <Rs>	-	1	Requires a register controlled
					shifted source register.
MOV <Rd>, <Rm>	1	-	<Rm>	1	Simple MOV case. Must not set the
					flags or require a shifted source
					register.

14.3.2Cycle counts if destination is the PC

Table 14-4shows the cycle timing behavior for data processing instructions if their destination is the PC. You can substitute ADD with any data processing instruction except for a CLZ. A CLZ with the PC as the destination is an Unpredictable instruction.

For condition code failing cycle counts, the cycles for the non-PC destination variants must be used.

Table 14-4 Data Processing instruction cycle timing behavior if destination is the PC

Example instruction	Cycles	Early	Late	Result	Comments
		Reg	Reg	latency
ADD pc, <Rn>, #<immed>	9	-	-	-	Normal cases to PC
ADD pc, <Rn>, <Rm>	9	-	-	-
ADD pc, <Rn>, <Rm>, LSL #<immed>	9	<Rm>	-	-	Requires a shifted source register
ADD pc, <Rn>, <Rm>, LSL <Rs>	9	<Rm>,	-	-	Requires a register controlled shifted
		<Rs>			source register

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