ARM R4F, r1p3 manual Memory types, Using memory types

Memory Protection Unit

7.2Memory types

The ARM Architecture defines a set of memory types with characteristics that are suited to particular devices. There are three mutually exclusive memory type attributes:

•Strongly Ordered

•Device

•Normal.

MPU memory regions can each be assigned a memory type attribute. Table 7-2shows a summary of the memory types.

Table 7-2 Memory attributes summary

Memory	Shared or
type		Other attributes	Description
	Non-shared
attribute
Strongly	-	-	All memory accesses to Strongly Ordered memory occur in
Ordered			program order. All Strongly Ordered accesses are assumed to
			be shared.
Device	Shared	-	For memory-mapped peripherals that several processors share.
	Non-shared	-	For memory-mapped peripherals that only a single processor
			uses.
Normal	Shared	Non-cacheable	For normal memory that is shared between several processors.
		Write-through Cacheable
		Write-back Cacheable
	Non-shared	Non-cacheable	For normal memory that only a single processor uses.
		Write-through Cacheable
		Write-back Cacheable

Note

The processor’s L1 cache does not cache shared normal regions.

For more information on memory attributes and types, memory barriers, and ordering requirements for memory accesses, see the ARM Architecture Reference Manual and Application Note 204, Understanding processor memory types and access ordering.

7.2.1Using memory types

The processor's memory system contains a store buffer which helps to improve the throughput of accesses to Normal type memory. See Store buffer on page 8-18for more information. Because of the ordering rules which they must follow, accesses to other types of memory typically have a lower throughput or higher latency than accesses to Normal memory. In particular:

•reads from Device memory must first drain the store buffer of all writes to Device memory

•all accesses to Strongly Ordered memory must first drain the store buffer completely.

Similarly, when it is accessing Strongly Ordered or Device type memory, the processor's response to interrupts must be modified, and the interrupt response latency is longer. See Low interrupt latency on page 2-19for more information.

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