ARM r1p3, R4F manual Example 9-1 Write merging

Level Two Interface

Example 9-1 Write merging

MOV r0, #0x4000
STRH	r1, [r0, #0x18]; Store a halfword at									0x4018
STR	r2, [r0,		#0xC]	; Store a			word	at	0x400C
STMIA	r0,	{r4-r7}		;	Store	four words at				0x4000
STRB	r3,	[r0,	#0x1D];		Store	a	byte	at	0x401D

If the memory at address 0x4000 is marked as Strongly Ordered or Device type memory, the AXI transactions shown in Table 9-23are generated.

Table 9-23 AXI transactions for Strongly Ordered or Device type memory

AWADDRM	AWBURSTM	AWSIZEM	AWLENM	WSTRBM
0x4018	Incr	16-bit	1 data transfer	0b00000011
0x400C	Incr	32-bit	1 data transfer	0b11110000
0x4000	Incr	32-bit	4 data transfers	0b00001111
				0b11110000
				0b00001111
				0b11110000
0x401D	Incr	8-bit	1 data transfer	0b00100000

In the example above, each store instruction produces an AXI burst of the same size as the data written by the instruction.

Table 9-24shows a possible resulting transaction if the same memory is marked as Non-cacheable Normal, or Cacheable write-through.

Table 9-24 AXI transactions for Non-cacheable Normal or Cacheable write-through memory

AWADDRM	AWBURSTM	AWSIZEM	AWLENM	WSTRBM
0x4000	Incr	64-bit	4 data transfers	0b11111111
				0b11111111

0b00000000

0b00100011

In this example:

•The store buffer has merged the STRB and STRH writes into one buffer entry, and therefore a single AXI transfer, the fourth in the burst.

•The writes, which occupy three buffer entries, have been merged into a single AXI burst of four transfers.

•The write generated by the STR instruction has not occurred, because it was overwritten by the STM instruction.

•The write transfers have occurred out of order with respect to the original program order.

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