ARM R4F, r1p3 manual MPU Region Access Control Register bit functions, Tex

System Control Coprocessor

The MPU Region Access Control Registers are:

•read/write registers

•accessible in Privileged mode only.

Figure 4-36shows the arrangement of bits in the register.

31 13 12 11 10 8 7 6 5 3 2 1 0

Reserved

XN

AP

TEX

S C B

Reserved

Figure 4-36 MPU Region Access Control Register format

Table 4-33shows how the bit values correspond with the Region Access Control Register functions.

			Table 4-33 MPU Region Access Control Register bit functions
Bits	Field	Function
[31:13]	Reserved	SBZ.
[12]	XN	Execute never. Determines if a region of memory is executable:
		0	= all instruction fetches enabled
		1	= no instruction fetches enabled.
[11]	-	Reserved.
[10:8]	AP	Access permission. Defines the data access permissions. For more information on AP bit values
		see, Table 4-34.
[7:6]	Reserved	SBZ.
[5:3]	TEX	Type extension. Defines the type extension attributea.
[2]	S	Share. Determines if the memory region is Shared or Non-shared:
		0	= Non-shared.
		1	= Shared.
		This bit only applies to Normal, not Device or Strongly Ordered memory.
[1]	C	C bita:
[0]	B	B bita:

a. For more information on this region attribute, see Table 7-3 on page 7-9.

Table 4-34shows the AP bit values that determine the permissions for Privileged and User data access.

Table 4-34 Access data permission bit encoding

AP bit values	Privileged permissions	User permissions	Description
b000	No access	No access	All accesses generate a permission fault
b001	Read/write	No access	Privileged access only
b010	Read/write	Read-only	Writes in User mode generate permission
			faults

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