ARM r1p3, R4, R4F The MPU Region Access Control Registers are: read/write registers, Figure 4-36 shows the arrangement of bits in the register., Table4-33 shows how the bit values correspond with the Region Access Control Register

System Control Coprocessor
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The MPU Region Access Control Registers are:
• read/write registers
• accessible in Privileged mode only.
Figure 4-36 shows the arrangement of bits in the register.
Figure 4-36 MPU Region Access Control Register format
Table4-33 shows how the bit values correspond with the Region Access Control Register
functions.
Table4-34 shows the AP bit values that determin e the permissions for Privileged and User data
access.
Reserved BC
31 30
TEX S
12567811 1012
XN AP
Reserved
13
Table4-33 MPU Region Access Control Register bit functions
Bits Field Function
[31:13] Reserved SBZ.
[12] XN Execute never. Determines if a region of memory is executable:
0= all instruction fetches enabled
1= no instruction fetches enabled.
[11] - Reserved.
[10:8] AP Access permission. Defines the data access permissions. For more information on AP bit values
see, Table4-34.
[7:6] Reserved SBZ.
[5:3] TEX Type extension. Defines the type extension attributea.
[2] S Share. Determines if the memory region is Shared or Non-shared:
0 = Non-shared.
1 = Shared.
This bit only applies to Normal, not Device or Strongly Ordered memory.
[1] C C bita:
[0] B B bita:
a. For more information on this region attribute, see Table7-3 on page 7-9.
Table4-34 Access data permission bit encoding
AP bit values Privileged permissions User permissions Description
b000 No access No access All accesses generate a permission fault
b001 Read/write No access Privileged access only
b010 Read/write Read-only Writes in User mode generate permission
faults