ARM R4F, r1p3 manual 13shows the timing parameters for the AXI slave output ports

AC Characteristics

Table 15-12 AXI master output port timing parameters (continued)

Output delay		Output delay	Signal name
minimum		maximum
Clock uncertainty		60%	AWPROTM[2:0]
Clock uncertainty		60%	AWUSERM[4:0]
Clock uncertainty		60%	AWVALIDM
Clock uncertainty		60%	WIDM[3:0]
Clock uncertainty		60%	WDATAM[63:0]
Clock uncertainty		60%	WSTRBM[7:0]
Clock uncertainty		60%	WLASTM
Clock uncertainty		60%	WVALIDM
Write response channel
	Clock uncertainty	60%	BREADYM
	Clock uncertainty	60%	ARIDM[3:0]
	Clock uncertainty	60%	ARADDRM[31:0]
	Clock uncertainty	60%	ARLENM[3:0]
	Clock uncertainty	60%	ARSIZEM[2:0]
	Clock uncertainty	60%	ARBURSTM[1:0]
	Clock uncertainty	60%	ARLOCKM[1:0]
	Clock uncertainty	60%	ARCACHEM[3:0]
	Clock uncertainty	60%	ARPROTM[2:0]
	Clock uncertainty	60%	ARUSERM[4:0]
	Clock uncertainty	60%	ARVALIDM
	Clock uncertainty	60%	RREADYM
	Clock uncertainty	60%	AWPARITYM
	Clock uncertainty	60%	WPARITYM
	Clock uncertainty	60%	ARPARITYM
	Clock uncertainty	50%	AXIMPARERR[1:0]

Table 15-13shows the timing parameters for the AXI slave output ports.

Table 15-13 AXI slave output ports timing parameters

Output delay	Output delay	Signal name
minimum	maximum
Clock uncertainty	60%	AWREADYS
Clock uncertainty	60%	WREADYS
Clock uncertainty	60%	BIDS[7:0]

ARM DDI 0363E	Copyright © 2009 ARM Limited. All rights reserved.	15-9
ID013010	Non-Confidential, Unrestricted Access