ARM R4F, r1p3 manual 7 c9, Cycle Count Register, 8 c9, Event Selection Register

Events and Performance Monitor

Table 6-7shows how the bit values correspond with the PMNXSEL Register functions.

Table 6-7 Performance Counter Selection Register bit functions

Bits	Field	Function
[31:5]	Reserved	RAZ on reads, SBZP on writes
[4:0]	SEL	Counter select:
		b00000	= selects counter 0
		b00001	= selects counter 1
		b00010	= selects counter 2.

Any values programmed in the PMNXSEL Register other than those specified in Table 6-7are Unpredictable.

To access the PMNXSEL Register, read or write CP15 with:

MRC p15, 0, <Rd>, c9, c12, 5 ; Read PMNXSEL Register

MCR p15, 0, <Rd>, c9, c12, 5 ; Write PMNXSEL Register

6.3.7c9, Cycle Count Register

The Cycle CouNT (CCNT) Register counts clock cycles.

The CCNT Register is:

•A read/write register

•Always accessible in Privileged mode. The USEREN Register determines accessibility in User mode, see c9, User Enable Register on page 6-15.

To access the CCNT read or write CP15 with:

MRC p15, 0, <Rd>, c9, c13, 0 ; Read CCNT Register

MCR p15, 0, <Rd>, c9, c13, 0 ; Write CCNT Register

The Cycle Count Register must be disabled before software can write to it. Any attempt by software to write to this register when enabled is Unpredictable.

6.3.8c9, Event Selection Register

There are three Event Selection Registers in the processor, EVTSEL0 to EVTSEL2, each corresponding to one of the Performance Monitor Count (PMC) Registers, PMC0 to PMC2. Each register selects the events you want a PMC Register to count. The register to be accessed is determined by the value in the Performance Counter Selection Register.

The EVTSEL Register is:

•A read/write register

•Always accessible in Privileged mode. The USEREN Register determines accessibility in User mode, see c9, User Enable Register on page 6-15.

Figure 6-7 on page 6-14shows the bit arrangement for the EVTSELx Register.

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