Divide | ARM R4F, r1p3 specs

Cycle Timings and Interlock Behavior

14.8Divide

This section describes the cycle timing behavior of the UDIV and SDIV instructions.

The divider unit is separate to the main execute pipeline so the UDIV and SDIV instructions require one cycle to issue. They execute out-of-order relative to the rest of the pipeline, and require an additional issue cycle at the end of the divide operation to write the result to the destination register. This additional cycle is not required if the divide instruction fails its condition code.

Result Latency for a UDIV instruction A divided by B is given by:

Result latency = 3 + max (( clz(B) - clz(A) + 1) ,0) 2

Result Latency for a SDIV instruction A divided by B is given by:

Result latency = 4 + max (( clz(B) - clz(A) + 1) ,0) 2

Note

•A divide instruction that fails its condition code or attempts to divide by zero has a Result Latency of three.

•The value of the (clz(B) - clz(A) + 1)/2 component of these equations must be rounded down.

•The clz(x) function counts the number of leading zeros in the 32-bit value x. If x is negative, it is negated before this count occurs.

ARM DDI 0363E	Copyright © 2009 ARM Limited. All rights reserved.	14-14
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Contents

Cortex-R4 and Cortex-R4F Cortex-R4 and Cortex-R4F Technical Reference ManualCopyright 2009 ARM Limited. All rights reserved Cortex-R4 and Cortex-R4F Technical Reference Manual Chapter Introduction Chapter Processor Initialization, Resets, and Clocking Chapter AC Characteristics Appendix B ECC Schemes List of Tables Adfsr and Aifsr bit functions Dirty register format, with ECC 11-12 Example interlocks 14-11 Table A-18 FPU signals Table C-1 List of Figures Cache operations C7 format for Set and Way Vector Catch Register format 11-20 Preface Feedback on Product revision status Using this bookAbout this book Identifies the major revision of the product Conventions Typographical Timing diagrams Signals ARM publications Further readingThis section lists publications by ARM and by third parties Other publications Feedback on this product FeedbackARM welcomes feedback on this product and its documentation Feedback on this book Introduction About the processor About the architecture Debug on Components of the processorThis section describes the main components of the processor System control coprocessor on Interrupt handling on Load/store unit Data Processing UnitFloating Point Unit Prefetch unit Instruction and data caches Memory Protection UnitTCM interfaces AXI master interface Error correction and detection5 L2 AXI interfaces AXI slave interface ETM interface DebugSystem performance monitoring Real-time debug facilities VIC port System control coprocessorInterrupt handling Low interrupt latency Return from exception using data from the stack Changes APB Debug interface ETM interface Test interface Processor has the following interfaces for external accessExternal interfaces of the processor APB Debug interface Standby mode Power managementRun mode Shutdown mode Configurable options Configurable optionsAtcm FPU includeda BtcmVFP MPU B0TCMPCEN Configurable options at reset Feature Options RegisterAtcmpcen B1TCMPCEN B1TCMECEN AtcmecenB0TCMECEN Atcmrmw Execution pipeline stages Names of the pipeline stages and their functions areInstruction decode Execute stages First stage of data memory accessIss Write-back of data from the execution pipelines Redundant core comparison Test features Product documentation, design flow, and architecture DocumentationDesign flow Software configuration Build configurationConfiguration inputs Architectural information Advanced Microcontroller Bus Architecture protocol Product revision information Processor identification Variant field, Debug ID Register Variant field, Main ID RegisterRevision field, Main ID Register Revision field, Debug ID Register Program status registers on Programmer’s ModelRegisters on Exceptions on About the programmer’s model ARM state Switching stateInstruction set states Thumb state Operating modes Data types Byte-invariant big-endian format Memory formatsByte-invariantbig-endian format Little-endian format Little-endian format Registers Register set Register mode identifiers Mode Mode identifier General registers and program counter Program status registers N, Z, C, and V bits Q bit IT bits J bit DNM bitsGE bits I and F bits E bitA bit Non-maskable fast interrupts on M bits PSR mode bit valuesM40 Mode Visible state registers Thumb Modification of PSR bits by MSR instructions ARM DDI 0363E Exception entry and exit summary Reset on Interrupts on Aborts onExceptions Exception entry and exit summary Taking an exception Leaving an exception Reset InterruptsInterrupt request Fast interrupt request Program status registers on Non-maskable fast interruptsNon-maskable fast interrupts Interrupt entry flowchart Interrupt controller Interrupt entry sequence Data aborts AbortsPrefetch aborts Precise aborts Imprecise aborts Aborts in Strongly Ordered and Device memory Abort handler Supervisor call instruction Undefined instruction Breakpoint instruction Exception vectors Acceleration of execution environments Unaligned and mixed-endian data access support Architecture Reference Manual Big-endian instruction support Reset modes on Processor Initialization, Resets, and ClockingResets on Initialization on 1 MPU InitializationCaches on TCM on 2 CRS Caches 5 TCMPreloading TCMs DMA into TCM Write to TCM directly from debuggerPreloading TCMs with parity or ECC Using TCMs from reset PRESETDBGn ResetsNRESET NSYSPORESET Reset modes Power-on reset Processor reset Normal operationHalt operation AXI interface clocking ClockingAXI interface clocking Clock gating Clock gating System Control Coprocessor About the system control coprocessor System control coprocessor functional groups System control coprocessor register functions Function Register/operation Reference to descriptionFcse PID TCM control TCM Status System control and configurationConfiguration Region System performance Performance monitoring MPU control and configuration Cache control and configuration TCM control and configuration System performance monitor System validation System performance monitor registers ARM DDI 0363E System control coprocessor registers Register allocationRAZ Control Undefined MPU Memory Region Read/write Enable Undefined MPU Region Access Read/writeUndefined MPU Region Size Read/write Number ARM DDI 0363E Undefined C3-c11 C12 Performance Monitor Read/write Event Select Read/write Unpredictable Performance MonitorCount Undefined RAZ,ignore C14 User Enable Read/writeUndefined C1-c15 C12 C0-c15 C13 Writes Context ID Read/write 2 c0, Main ID Register 7shows the arrangement of bits in the register 3 c0, Cache Type Register Main ID Register bit functionsBits Field Function Cache Type Register bit functions Bits Field Function To access the Cache Type Register, read CP15 with4 c0, TCM Type Register TCM Type Register bit functions Bits Field Function 5 c0, MPU Type Register To access the TCM Type Register, read CP15 withTo access the MPU Type Register, read CP15 with TCM Type Register bit functions Processor Feature Registers C0, Processor Feature Register 0, PFR06 c0, Multiprocessor ID Register Processor Feature Register 0 bit functions To access the Processor Feature Register 0 read CP15 withC0, Processor Feature Register 1, PFR1 Processor Feature Register 1 bit functions Debug Feature Register 0 bit functions To access the Processor Feature Register 1 read CP15 with8 c0, Debug Feature Register 3124 Reserved Memory Model Feature Registers To access the Debug Feature Register 0 read CP15 with9 c0, Auxiliary Feature Register C0, Memory Model Feature Register 0, MMFR0 C0, Memory Model Feature Register 1, MMFR1 10 Memory Model Feature Register 0 bit functions 16 Memory Model Feature Register 1 format 11 Memory Model Feature Register 1 bit functions C0, Memory Model Feature Register 2, MMFR2 WFIDMB C0, Memory Model Feature Register 3, MMFR3 13 Memory Model Feature Register 3 bit functions3112 Reserved Instruction Set Attributes Registers C0, Instruction Set Attributes Register 0, ISAR014 Instruction Set Attributes Register 0 bit functions C0, Instruction Set Attributes Register 1, ISAR1 20 Instruction Set Attributes Register 1 format C0, Instruction Set Attributes Register 2, ISAR2 ITEIndicates support for if then instructions 16 Instruction Set Attributes Register 2 bit functions PSRIndicates support for PSR instructions C0, Instruction Set Attributes Register 3, ISAR3 17 Instruction Set Attributes Register 3 bit functionsThumb instruction sets C0, Instruction Set Attributes Register 4, ISAR4 23 Instruction Set Attributes Register 4 format C0, Instruction Set Attributes Registers 12 c0, Current Cache Size Identification Register18 Instruction Set Attributes Register 4 bit functions 4KB 8KB 13 c0, Current Cache Level ID Register 3130 Reserved 14 c0, Cache Size Selection Register 15 c1, System Control Register TRE 23 System Control Register bit functionsAFE Nmfi = data caching enabled Enables L1 data cache= data caching disabled. This is the reset value = strict alignment fault checking enabled Auxiliary Control Registers C1, Auxiliary Control Register24 Auxiliary Control Register bit functions Dilsm AxiscenAxiscuen Deolp Dlfo RsdisDbwr Dnch C15, Secondary Auxiliary Control Register 25 Secondary Auxiliary Control Register bit functions OFC DoofmacsIXC UFC Primary input RMWENRAM0 defines the reset value 17 c1, Coprocessor Access RegisterPrimary input RMWENRAM1 defines the reset value Atcmecc Fault Status and Address Registers C5, Data Fault Status RegisterAll other encodings for these FSR bits are Reserved C5, Instruction Fault Status Register 28 Data Fault Status Register bit functionsTo use the Dfsr read or write CP15 with There are two auxiliary fault status registers To access the Ifsr read or write CP15 withC5, Auxiliary Fault Status Registers 29 Instruction Fault Status Register bit functions = Atcm C6, Data Fault Address Register30 Adfsr and Aifsr bit functions = Btcm C6, Instruction Fault Address Register 19 c6, MPU memory region programming registers C6, MPU Region Size and Enable Registers C6, MPU Region Base Address Registers C6, MPU Region Access Control Registers 158 Sub-region disable32 Region Size Register bit functions 33 MPU Region Access Control Register bit functions TEX UNP 34 Access data permission bit encodingC6, MPU Memory Region Number Register 35 MPU Memory Region Number Register bit functions Cache operations Point of Coherency PoCPoint of Unification PoU Invalidate and clean operations Set and Way format 36 Functional bits of c7 for Set and Way 37shows the cache sizes and the resultant bit range for SetAddress format 37 Widths of the set field for L1 cache sizes Size Set 21 c9, Btcm Region Register Data Synchronization Barrier operationData Memory Barrier operation 38 Functional bits of c7 for address format Bits Field To access the Btcm Region Register, read or write CP15 with 22 c9, Atcm Region Register39 Btcm Region Register bit functions 24 c11, Slave Port Control Register To access the Atcm Region Register, read or write CP15 with23 c9, TCM Selection Register 40 Atcm Region Register bit functions 312 Reserved 25 c13, Fcse PID Register26 c13, Context ID Register RAZ/UNP 27 c13, Thread and Process ID Registers C15, nVAL IRQ Enable Set Register Validation RegistersCcnt overflow IRQ request C15, nVAL FIQ Enable Set Register Ccnt overflow FIQ request C15, nVAL Reset Enable Set Register C15, nVAL Debug Request Enable Set RegisterCcnt overflow reset request C15, nVAL IRQ Enable Clear Register Ccnt overflow debug request C15, nVAL FIQ Enable Clear Register 48 nVAL IRQ Enable Clear Register format C15, nVAL Reset Enable Clear Register 303 Reserved UNP or Sbzp C15, nVAL Debug Request Enable Clear Register 51 nVAL Debug Request Enable Clear Register format 318 Reserved C15, nVAL Cache Size Override Register50 nVAL Cache Size Override Register B0000 4kB B0001 8kB B0011 16kB B0111 32kB B1111 64kB Correctable Fault Location Register 53 Correctable Fault Location Register cache 52 Correctable Fault Location Register cache C15, Build Options 1 Register To access the Build Options 1 Register, write CP15 withBuild Options Registers C15, Build Options 2 Register Nodcache 55 Build Options 2 RegisterNoicache Atcmes Nofpu BtcmesNoie Nompu Dcachees To access the Build Options 2 Register, write CP15 withNoharderrorcach Axibusparity Prefetch Unit About the prefetch unit Branch prediction Disabling program flow prediction Configuring the branch predictor Branch predictorIncorrect predictions and correction Return stack Events and Performance Monitor Event bus interface bit functions Bit position Update ValueAbout the events Event ETMEXTOUT0 ETMEXTOUT1 But with different attributes Dual issue case a branch Non-cacheable access on AXI master busInstruction cache access Dual issue case B1, B2, F2 load/store, F2D TCM correctable ECC error reported by load/store unit Yes TCM correctable ECC error reported by prefetch unit Yes About the PMU 1 c9, Performance Monitor Control Register Performance monitoring registersPerformance monitoring registers are described 2shows how the bit values correspond with the Pmnc Register 2 c9, Count Enable Set Register Pmnc Register bit functions To access the Cntens Register, read or write CP15 with 3 c9, Count Enable Clear RegisterCntens Register bit functions Bits Field Function 4 c9, Overflow Flag Status Register To access the Cntenc Register, read or write CP15 withCycle counter enable clear Cntenc Register bit functions Bits Field Function To access the Flag Register, read or write CP15 with 5shows how the bit values correspond with the Flag Register5 c9, Software Increment Register Swincr Register bit functions Bits Field Function To access the Swincr Register, read or write CP15 with6 c9, Performance Counter Selection Register 313 Reserved RAZ on reads, Sbzp on writes Increment Counter 7 c9, Cycle Count Register 8 c9, Event Selection RegisterSEL To access the EVTSELx Register, read or write CP15 with EVTSELx Register bit functions 10 c9, User Enable Register 9 c9, Performance Monitor Count RegistersUseren Register bit functions 11 c9, Interrupt Enable Set Register Ccnt overflow interrupt enable10 Intens Register bit functions Bits Field Function 12 c9, Interrupt Enable Clear Register Ccnt overflow interrupt enable bit11 Intenc Register bit functions Bits Field Function To access the Intenc Register, read or write CP15 with Event bus interface Use of the event bus and counters MPU faults on MPU software-accessible registers onMemory Protection Unit Default memory map About the MPUTrue Region size Memory regionsRegion base address Subregions Overlapping regions Region access permissionsRegion attributes Region Example of using regions that overlap Example of using subregions Background regions TCM regions Using memory types Memory types ARM DDI 0363E Region attributes TEX20, C, and B encodings Description Memory Type Shareable? Cacheable memory policies 1BB On page 7-2shows the default memory map MPU interaction with memory systemFollowing code is an example of disabling the MPU Background fault MPU faultsBackground fault Permission fault Alignment fault Permission fault MPU software-accessible registers On page 4-5shows the CP15 registers that control the MPU Level One Memory System About the L1 memory system L1 memory system block diagram About the error detection and correction schemes Parity Bit ECC onParity Bit ECC Error checking and correctionHard errors Read-Modify-Write Error correction Correct inlineCorrect-and-retry Classes of fault that can occur are Fault handlingFaults MPU faults External faults Cache and TCM parity and ECC errorsTCM external faults Precise and imprecise aborts Fault status informationDebug events Abort exceptions Precise abort exceptions Imprecise abort exceptionsUsage models Correctable errors Types of aborts Conditions Source Precise FatalAXI ARM DDI 0363E About the TCMs TCM attributes and permissions Atcm and Btcm configuration TCM internal error detection and correctionHandling TCM parity errors on Handling TCM ECC errors on Handling TCM parity errors Handling TCM ECC errorsTCM arbitration External TCM errors TCM initializationTCM port protocol AXI slave interfaces for TCMs About the caches Store buffer Store buffer behavior Cache maintenance operationsStore buffer merging Store buffer draining Cache error detection and correction Error build options Address decoder faults Handling cache parity errorsCache parity error behavior Value Behavior Handling cache ECC errors Cache ECC error behavior Value Behavior Errors on data cache write Errors on instruction cache readErrors on data cache read Errors on evictions Invalidate all instruction cache Clean data cache by set/way Dirty RAM on Data RAM on Cache RAM organizationTag RAM Tag RAM Cache sizes and tag RAM organization Tag RAM organization Dirty RAMData RAM Organization of a dirty RAM line Nonsequential read operation performed with one RAM access Data RAM sizes without parity or ECC implemented 13 Data cache RAM bits, with parity Description Following code is an example of enabling caches Cache interaction with memory systemDisabling or enabling all of the caches 15 Data cache data RAM sizes with ECC Cache size Data RAMs Disabling or enabling error checking Disabling or enabling instruction cacheDisabling or enabling data cache MCR p15 R0, c1 Write System Control Register Internal exclusive monitor Memory types and L1 memory system behavior Instruction-cache error events Error detection eventsTCM error events Data-cache error events ARM DDI 0363E Level Two Interface About the L2 interface AXI master interface 1shows the AXI master interface attributesAttribute Value Comments Outstanding write accesses with the same ID Identifiers for AXI bus accessesOutstanding write/read access on different IDs Write response Arcachem and Awcachem encodings Encoding a Meaning Eviction bufferMemory attributes Aruserm and Awuserm encodings Memory system implications for AXI accesses AXI master interface transfers Strongly Ordered and Device transactions onLinefills on Non-cacheable Ldrb Restrictions on AXI transfersStrongly Ordered and Device transactions Address20 LDR or LDM that transfers one register Ldrh from Strongly Ordered or Device memory Address30 LDM that transfers five registers LDM5, Strongly Ordered or Device memory Address40 Strb to Strongly Ordered or Device memory Address40 Strh to Strongly Ordered or Device memory Address20 STR or STM of one register STM of seven registersFirst Wstrbm Linefills Cache line write-back evictionNon-cacheable reads 14 Ldrh from Non-cacheable Normal memory Address20 15 LDR or LDM1 from Non-cacheable Normal memory Address20 Non-cacheable or write-through writes AXI transaction splitting Normal write merging 20 AXI transaction splitting, data in two cache lines Example 9-1 Write merging ARM DDI 0363E AXI slave interface AXI slave interface for cache RAMs TCM parity and ECC support Cache parity and ECC supportAXI slave control AXI slave characteristics 25 AXI slave interface attributes Enabling or disabling AXI slave accesses Accessing RAMs using the AXI slave interface TCM RAM access on Cache RAM access on26 RAM region decode AxUSERS bit One-hot RAM select 27 TCM chip-select decode Btcm ports TCM RAM accessARADDRSMSB, see Table RAM selected Cache RAM access Memory map when accessing the cache RAMsThis section contains the following 31 Cache data RAM bank/address decode Inputs ARADDRS1815 Data RAM access0010 Bank 0100 1000 0001 Bank 0010 0100 1000 34 Data format, instruction cache, with ECC 35 Data format, data cache, with ECC Data bit Description Tag RAM access ARM DDI 0363E Dirty RAM access 43 Dirty register format, with ECC Data bit Description Other examples of accessing cache RAMs ARADDRS1815 = 4b1111 Power Control About power control on Power management on About power control Dormant mode Run modeStandby mode Shutdown mode Communication to the Power Management Controller Debug Debug state on Cache debug on Debug host Debug systemsDebug host Protocol converter Debug target Protocol converter Monitor debug-mode debugging About the debug unitHalting debug-mode debugging Programming the debug unit All other state information associated with the debug unit Coprocessor registers 11.3.2 CP14 access permissionsDebug register interface Coprocessor registers summary Instruction Mnemonic Description Offset Register Access Mnemonic Description Hex NumberMemory-mapped registers Debug memory-mapped registers Memory addresses for breakpoints and watchpoints APB port access permissions Power domainsEffects of resets on debug registers Privilege of memory access permission Other Debug registers External debug interface access permissions RegistersLock Other registers 6shows the CP14 debug register map Accessing debug registersDebug register descriptions 11.4.2 CP14 c0, Debug ID Register Debug ID Register functions WRPBRP To use the Debug ROM Address Register, read CP14 c0 with To use the Debug ID Register, read CP14 c0 with11.4.3 CP14 c0, Debug ROM Address Register 11.4.4 CP14 c0, Debug Self Address Offset Register Debug Self Address Offset Register format Debug Self Address Offset Register functions 11.4.5 CP14 c1, Debug Status and Control Register 10 Debug Status and Control Register functions Flag is set to 1 on entry to debug state Execute ARM instruction enable bit = disabled, this is the reset valueARM DTR access mode MOE Data Transfer Register Vector Catch Register Watchpoint Fault Address Register12 Watchpoint Fault Address Register functions Reserved RAZ SVC Instruction Transfer Register Bits Field Reset Description ValueDebug State Cache Control Register 14 Debug State Cache Control Register functions Debug Run Control Register 15 Debug Run Control Register functions315 Reserved Breakpoint Value Registers Breakpoint Control Registers 17 Breakpoint Control Registers functions 18 Meaning of BVR bits +0 is accessedCorresponding instruction address breakpoint BVR2220 Meaning Watchpoint Value Registers Watchpoint Control Registers19 Watchpoint Value Registers functions Bits Description 11 Watchpoint Control Registers format 20 Watchpoint Control Registers functions Accessed Operating System Lock Status Register Authentication Status Register 21 OS Lock Status Register functions = Dbgnopwrdwn is LOW. This is the reset value Device Power-down and Reset Control RegisterDevice Power-down and Reset Status Register 23 Prcr functions 15 Prsr format 24 Prsr functions Management registers Processor ID Registers Claim Registers Claim Tag Set Register27 Claim Tag Set Register functions Bits Field Function Claim Tag Clear Register Lock Access Register318 Reserved RAZ or Sbzp Claim tag clear Reset value is Lock Status Register Device Type Register Debug Identification Registers30 Device Type Register functions 33 Peripheral ID Register 0 functions 32 Fields in the Peripheral Identification RegistersField Size Description Bits Value Description 36 Peripheral ID Register 3 functions 34 Peripheral ID Register 1 functions35 Peripheral ID Register 2 functions 37 Peripheral ID Register 4 functions 1021 1020Component Identification Register 1022 Debug events Software debug event Debug event priority Halting debug eventBehavior of the processor on debug events Watchpoint debug events Debug exception Effect of debug exceptions on CP15 registers and Wfar 40shows the values in the link register after exceptionsFollowing sections describe Four CP15 registers that record abort information are Avoiding unrecoverable states Entering debug state Debug statePrivilege on 41 Read PC value after debug state entry Behavior of the PC and Cpsr in debug state 41 Read PC value after debug state entry Debug event Writing to the Cpsr in debug state Accessing registers and memoryExecuting instructions in debug state Privilege Effects of debug events on processor registers Coprocessor instructionsEffect of debug state on non-invasive debug Exceptions in debug state Imprecise Data Aborts on entry and exit from debug state Precise Data abortImprecise Data Abort Leaving debug state Sets the DSCR1 core restarted flag to Cache pollution in debug state Cache debugThis section describes cache debug. It consists Cache coherency in debug state This section describes the miscellaneous debug signals APB signalsMiscellaneous debug signals External debug interface 42 Authentication signal restrictions Dbgen a Authentication signalsChanging the authentication signals Non-invasive debug permitted Issue an Instruction Synchronization Barrier ISB instruction Using the debug functionality Example 11-1 Executing an ARM instruction through the ITR Rules for accessing the DCC Debug communications channel Example 11-5shows the code for host-to-target data transfer Software access to the DCCDebugger access to the DCC Example 11-4 Target to host data transfer host end Programming simple breakpoints and the byte address select Programming breakpoints and watchpointsThis section describes the following operations Example 11-6 Polling the DCC host end Setting a simple aligned watchpoint Example 11-7 Setting a simple breakpoint Setting a simple unaligned watchpoint Example 11-8 Setting a simple aligned watchpoint Single-stepping Example 11-9 Setting a simple unaligned watchpoint45shows some examples Not required Debug state entry Example 11-10 Single-stepping off an instructionExample 11-11 Entering debug state Debug state exit Example 11-12 Leaving debug state Reading and writing registers through the DCC Accessing registers and memory in debug stateThis section describes the following Example 11-13 Reading an ARM register Reading the Cpsr in debug state Reading the PC in debug stateExample 11-15shows the code to read the PC Example 11-16shows the code for reading the Cpsr Example 11-18shows the code for reading a byte of memory Example 11-19 Checking for an abort after memory accessReading memory Example 11-17 Writing the Cpsr Example 11-20 Reading a block of bytes of memory Example 11-21 Reading a word of memory Example 11-24 Writing registers in stall mode Example 11-22 Changing the DTR access modeExample 11-23 Reading registers in stall mode Fast register read/write Fast memory read/write Example 11-25 Reading a block of words of memory Accessing coprocessor registers Example 11-27 Reading a coprocessor register 11-70 Emulating power down Debugging systems with energy management capabilities 11-72 FPU Programmer’s Model About the FPU programmer’s model FPU functionalityAbout the VFPv3-D16 architecture General-purpose registers FPU views of the register bank System registers VFPv3 architecture describes the following system registers1shows the VFP system registers in the Cortex-R4F FPU Mvfr registers are privileged access only All hardware ID information is privileged access onlyFpsid is privileged access only This is a change in VFPv3 compared to VFPv2 DNM Floating-Point Status and Control Register, FpscrFpscr Register bit functions Rmode IDE RAZ Floating-Point Exception Register, FpexcLEN DNM IXE RAZ UFE OFE DZE IOE IDC DEX Media and VFP Feature Registers, MVFR0 and MVFR1Floating-Point Exception Register bit functions MVFR0 Register bit functions MVFR1 Register bit functions Full denormal arithmetic supported for VFP Flush-to-zero mode Full-compliance mode Flush-to-zero mode Default NaN modeFull-compliance mode Default NaN mode Ieee 754 standard implementation choices Compliance with the Ieee 754 standardComplete implementation of the Ieee 754 standard NaN handling QNaN and SNaN handling ComparisonsUnderflow CDP Exceptions Integration Test Registers About Integration Test Registers Software access using APB Programming and reading Integration Test Registers Itmiscout Register ItctrlItetmif Itmiscin Processor integration testing 13121110 Using the Integration Test Registers Performing integration testing Itetmif Register ETM interface Itetmif Register bit assignments Bits Name Function Itmiscout Register Miscellaneous Outputs Itmiscin Register Miscellaneous InputsItmiscout Register bit assignments Bits Name Function Dbgrestart Integration Mode Control Register ItctrlBits Name Function Etmextout RAZ/SBZP Bits Access Reset value Name Function7shows the fields of the Itctrl Register Intmode Cycle Timings and Interlock Behavior Multiplies on Divide on Branches on Dual issue on About cycle timings and interlock behavior Instruction execution overview Conditional instructions Following sequence where R1 is a Late Reg takes two cyclesFlag-setting instructions Definition of terms Assembler language syntax Takes two cycles because there are no register dependencies Register interlock examplesInstruction Behavior Sequence Takes three cycles because of the result latency of R1 Data processing instructions Cycle counts if destination is not PCCycle counts if destination is the PC Example interlocks ShifterRegister controlled shifts QADD, QDADD, QSUB, and Qdsub instructions Media data-processing SEL Result of the USAD8 instruction Sum of Absolute Differences SADInstruction sequence Behavior USAD8 instruction Multiplies Umlals 14-13 Divide Branches 10 Branch instruction cycle timing behaviorExample instruction Cycles Memory Comments All MRS instructions Mode changingProcessor state updating instructions All MSR instructions to the Spsr Single load and store instructions 13shows the cycle timing behavior for loads to the PC Base register update 13 Cycle timing behavior for loads to the PCExample instruction Cycles Memory Result Comments Latency 14-19 Register offset, then 3-issue cycles Load and Store Double instructions Load and Store Multiple instructions Write-back Return stack prediction Load Multiples, where the PC is in the register listCorrect condition prediction and correct Correct condition prediction and incorrect 14-23 RFE and SRS instructions Synchronization instructions Clrex Coprocessor instructions Some instructions such as cache operations take more cycles SVC formerly SWI Prefetch Abort Undefined Instruction Miscellaneous instructions Floating-point register transfer instructions Blocking and serializingSerializing Not aligned Floating-point load/store instructionsBit aligned address 2,2 2,3 4,5 Floating-point single-precision data processing instructions Floating-point double-precision data processing instructions Dual issue Dual issue rules Permitted combinations onDual issue rules Dual issue First instruction Second instruction Case Permitted combinations28 Permitted instruction combinations Multiply-accumulate instructionso Case F2stbAny single-precision CDPi, excluding Case F2Db AC Characteristics Processor timing on Processor timing parameters on Processor timing Clock uncertainty 10% Processor timing parametersInput port timing parameters Clock uncertainty 50% 3shows the timing parameters for the interrupt input ports 4shows the input timing parameters for the AXI master portClock uncertainty 60% 5shows the input timing parameters for the AXI slave port Rreadys 6shows the input timing parameters for the debug input ports 7shows the input timing parameters for the ETM input ports 8shows the timing parameters for the test input ports Clock uncertainty 65%Clock uncertainty 40% Output ports timing parameters 11shows the timing parameters for the interrupt output ports 13shows the timing parameters for the AXI slave output ports Write response channel Clock uncertainty 60% BRESPS10 16shows the timing parameters for the test output ports Clock uncertainty 45% 18shows the timing parameters for the FPU output signals Fpidc 15-13 Processor Signal Descriptions FPU signals on page A-23 About the processor signal descriptions AnyFrom any clock Global signals Table A-1 Global signalsSignal Direction Clocking Description Table A-2 Configuration signals Configuration signalsTable A-2shows the processor configuration signals Information Tie LOW for even parity Tie High for odd parity RMWENRAM10b Interrupt signals, including VIC interface signals L2 interface signals Table A-4 AXI master port signals for the L2 interfaceAXI master port Identification tag for the read address group of signals Identification tag for the write data group of signalsIdentification tag for the write response signal Protection signals provide addition information about a bus Table A-6 AXI slave port signals for the L2 interface AXI master port error detection signalsTable A-5 AXI master port error detection signals AXI slave port Protection information, privileged/normal access. ARPROT0 Protection information, privileged/normal access. AWPROT0AXI specification One to 16. a four bit binary value minus one determines Standard AXI specification AXI slave port error detection signalsATCM, one hot. AWUSERS30 signal is not part Table A-7 AXI slave port error detection signals TCM interface signals Table A-8shows the Atcm port signalsTable A-9shows the B0TCM port signals Table A-10shows the B1TCM port signals Table A-10 B1TCM port signals= DMA Write data for B1TCM data RAM B1TCM RAM access is sequentialAddress for B1TCM data RAM Write parity or ECC code for B1TCM Dual core interface signals Table A-11shows the dual redundant core interface signalsTable A-11 Dual core interface signals Debug interface signals Table A-13shows the debug miscellaneous signalsTable A-12 Debug interface signals Input Tie-off Debug self-address offset Table A-13 Debug miscellaneous signalsInput Tie-off Debug ROM physical address valid Input Tie-off Debug self-address offset valid ETM interface signals Table A-14shows the ETM interface signalsTable A-14 ETM interface signals Test signals Table A-15shows the test signalsTable A-15 Test signals Mbist signals Table A-16shows the Mbist signals Validation signals Table A-17shows the validation signals FPU signals Table A-18 FPU signals ECC Schemes ECC scheme selection guidelines on page B-2 ECC scheme selection guidelines Clarified byte-invariant big-endian format NCPUHALT removed from timing diagram Added sectionsRevisions Clarified little-endian format Table C-1 Differences between issue B and issue C Change Location Table C-2 Differences between issue C and issue D No technical changes See also Data Abort, External Abort and Prefetch Abort GlossaryAbort, and an internal or External Abort Base register write-back That are divisible by four and two respectively See also Advanced High-performance BusSee Advanced High-performance Bus See Advanced Microcontroller Bus Architecture Active write transaction Active read transactionActive transfer Completed transfer Write ID capability Read ID widthRead issuing capability Write ID width See also Burst See also Beat See also Word-invariant Accesses are expected to be word-alignedAccessed in parallel during a cache look-up Bus See also Dirty See also Clean See Embedded Trace Macrocell Option chosen does not affect software compatibility An instruction that is architecturally UndefinedBy individual implementations Precision and the fraction is all zeros See Cold reset Serviced while normal program execution is suspendedSee also Halt mode Result of attempting to access invalid instruction memory See Should Be Zero Or equal to 1 and is not restricted to being a power of twoSee Should Be One See Boundary scan chain Destination precision See Debug test access portIncrement of +2 User trap handler is executed Processor-specific. a victim is also known as a cast out Expected behavior for an unaligned accessBit for the exception is set A processor Cache terminology diagram

ARM R4F, r1p3 manual Divide

Models: R4F r1p3 R4

14.8Divide

ARM DDI 0363E