Cycle Timings and Interlock Behavior

14.2Register interlock examples

Table 14-2shows register interlock examples using LDR and ADD instructions.

LDR instructions take one cycle, have a result latency of two, and require their base register as a Very Early Reg.

ADD instructions take one cycle and have a result latency of one.

 

Table 14-2 Register interlock examples

 

 

Instruction

Behavior

sequence

 

 

 

LDR R1, [R2]

Takes two cycles because there are no register dependencies.

ADD R6, R5, R4

 

 

 

ADD R1, R2, R3

Takes two cycles because ADD instructions have a result latency of one.

ADD R9, R6, R1

 

 

 

LDR R1, [R2]

Takes three cycles because of the result latency of R1.

ADD R6, R5, R1

 

 

 

ADD R2, R5, R6

Takes four cycles because of the use of the result of R2 as a Very Early Reg.

LDR R1, [R2]

 

 

 

LDR R1, [R2]

Takes four cycles because of the result latency of R1, the use of the result of R1 as a Very Early Reg,

LDR R5, [R1]

and the use of an LDR to generate R1.

 

 

ARM DDI 0363E

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14-6

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Image 370
ARM R4 Register interlock examples, Instruction Behavior Sequence, Takes three cycles because of the result latency of R1