ARM R4F, r1p3 manual System control coprocessor register functions, Fcse PID

System Control Coprocessor

		Table 4-1 System control coprocessor register functions
Function	Register/operation		Reference to description
System control and	Control		c1, System Control Register on page 4-35
configuration
	Auxiliary control		Auxiliary Control Registers on page 4-38
	Coprocessor Access Control		c1, Coprocessor Access Register on page 4-44
	Main IDa		c0, Main ID Register on page 4-14
	Product Feature IDs		The Processor Feature Registers on page 4-18
			c0, Debug Feature Register 0 on page 4-20
			c0, Auxiliary Feature Register 0 on page 4-21
			Memory Model Feature Registers on page 4-21
			Instruction Set Attributes Registers on page 4-26
	Multiprocessor ID		c0, Multiprocessor ID Register on page 4-18
	Slave Port Control		c11, Slave Port Control Register on page 4-59
	Context ID		c13, Context ID Register on page 4-60
	FCSE PID		c13, FCSE PID Register on page 4-60
Software compatibility	Thread And Process ID		c13, Thread and Process ID Registers on page 4-61
MPU control and	Data Fault Status		c5, Data Fault Status Register on page 4-45
configuration
	Auxiliary Fault Status		c5, Auxiliary Fault Status Registers on page 4-47
	Instruction Fault Status		c5, Instruction Fault Status Register on page 4-46
	Instruction Fault Address		c6, Instruction Fault Address Register on page 4-49
	Data Fault Address		c6, Data Fault Address Register on page 4-48
	MPU Type		c0, MPU Type Register on page 4-17
	Region Base Address		c6, MPU Region Base Address Registers on page 4-50
	Region Size and Enable		c6, MPU Region Size and Enable Registers on page 4-50
	Region Access Control		c6, MPU Region Access Control Registers on page 4-51
	Memory Region Number		c6, MPU Memory Region Number Register on page 4-53
Cache control and	Cache Type		c0, Cache Type Register on page 4-15
configuration
	Current Cache Size		c0, Current Cache Size Identification Register on page 4-32
	Identification
	Current Cache Level		c0, Current Cache Level ID Register on page 4-34
	Cache Size Selection		c0, Cache Size Selection Register on page 4-35
	c7, Cache Operations		Cache operations on page 4-54
	c15, Invalidate all data cache

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