ARM r1p3 Bit for the exception is set, Processor-specific. a victim is also known as a cast out

	Glossary
Unsupported values	Specific data values that are not processed by the hardware but bounced to the support code for
	completion. These data can include infinities, NaNs, subnormal values, and zeros. An
	implementation is free to select which of these values is supported in hardware fully or partially,
	or requires assistance from support code to complete the operation. Any exception resulting
	from processing unsupported data is trapped to user code if the corresponding exception enable
	bit for the exception is set.
Victim	A cache line, selected to be discarded to make room for a replacement cache line that is required
	as a result of a cache miss. The way in which the victim is selected for eviction is
	processor-specific. A victim is also known as a cast out.
Warm reset	Also known as a core reset. Initializes the majority of the processor excluding the debug
	controller and debug logic. This type of reset is useful if you are using the debugging features
	of a processor.
Watchpoint	A watchpoint is a mechanism provided by debuggers to halt program execution when the data
	contained by a particular memory address is changed. Watchpoints are inserted by the
	programmer to enable inspection of register contents, memory locations, and variable values
	when memory is written to test that the program is operating correctly. Watchpoints are removed
	after the program is successfully tested. See also Breakpoint.
Way	See Cache way.
WB	See Write-back.
Word	A 32-bit data item.
Word-invariant	In a word-invariant system, the address of each byte of memory changes when switching
	between little-endian and big-endian operation, in such a way that the byte with address A in
	one endianness has address A EOR 3 in the other endianness. As a result, each aligned word of
	memory always consists of the same four bytes of memory in the same order, regardless of
	endianness. The change of endianness occurs because of the change to the byte addresses, not
	because the bytes are rearranged. The ARM architecture supports word-invariant systems in
	ARMv3 and later versions. When word-invariant support is selected, the behavior of load or
	store instructions that are given unaligned addresses is instruction-specific, and is in general not
	the expected behavior for an unaligned access.
	See also Byte-invariant.
Write	Writes are defined as operations that have the semantics of a store. That is, the ARM instructions
	SRS, STM, STRD, STC, STRT, STRH, STRB, STRBT, STREX, SWP, and SWPB, and the Thumb instructions STM,
	STR, STRH, STRB, and PUSH.
Write-back (WB)	In a write-back cache, data is only written to main memory when it is forced out of the cache on
	line replacement following a cache miss. Otherwise, writes by the processor only update the
	cache. Also known as copyback.
Write buffer	A block of high-speed memory, arranged as a FIFO buffer, between the data cache and main
	memory, whose purpose is to optimize stores to main memory.
Write completion	The memory system indicates to the processor that a write has been completed at a point in the
	transaction where the memory system is able to guarantee that the effect of the write is visible
	to all processors in the system. This is not the case if the write is associated with a memory
	synchronization primitive, or is to a Device or Strongly Ordered region. In these cases the
	memory system might only indicate completion of the write when the access has affected the
	state of the target, unless it is impossible to distinguish between having the effect of the write
	visible and having the state of target updated. This stricter requirement for some types of
	memory ensures that any side-effects of the memory access can be guaranteed by the processor
	to have taken place. You can use this to prevent the starting of a subsequent operation in the
	program order until the side-effects are visible.

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