ARM R4F, r1p3 manual Read ID width, Read issuing capability, Write ID capability, Write ID width

Glossary

Read ID width

	The number of bits in the ARID bus.
	Read issuing capability
	The maximum number of active read transactions that a master interface can
	generate.
	Write ID capability
	The maximum number of different AWID values that a master interface can
	generate for all active write transactions at any one time.
	Write ID width
	The number of bits in the AWID and WID buses.
	Write interleave capability
	The number of active write transactions for which the master interface is capable
	of transmitting data. This is counted from the earliest transaction.
	Write issuing capability
	The maximum number of active write transactions that a master interface can
	generate.
	The following AXI terms are slave interface attributes. To obtain optimum performance, they
	must be specified for all components with an AXI slave interface
	Combined acceptance capability
	The maximum number of active transactions that a slave interface can accept.
	This is specified instead of write or read acceptance capability for slave interfaces
	that use a combined storage for active write and read transactions.
	Read acceptance capability
	The maximum number of active read transactions that a slave interface can
	accept.
	Read data reordering depth
	The number of active read transactions for which a slave interface can transmit
	data. This is counted from the earliest transaction.
	Write acceptance capability
	The maximum number of active write transactions that a slave interface can
	accept.
	Write interleave depth
	The number of active write transactions for which the slave interface can receive
	data. This is counted from the earliest transaction.
Banked registers	Those physical registers whose use is defined by the current processor mode. The banked
	registers are R8 to R14.
Base register	A register specified by a load/store instruction that is used to hold the base value for the
	instruction’s address calculation. Depending on the instruction and its addressing mode, an
	offset can be added to or subtracted from the base register value to form the virtual address that
	is sent to memory.

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