Processor Signal Descriptions

 

 

 

Table A-2 Configuration signals (continued)

 

 

 

 

Signal

Direction

Clocking

Description

 

 

 

 

ERRENRAM[2:0]

Input

Tie-off,

TCMs external error enable. Tie each bit high to enable the

 

 

Reset

external error signals for each TCM at reset. Use the following

 

 

 

values:

 

 

 

2: B1TCM

 

 

 

1: B0TCM

 

 

 

0: ATCM

 

 

 

See Auxiliary Control Registers on page 4-38for more

 

 

 

information.

 

 

 

 

RMWENRAM[1:0]b

Input

Tie-off,

RMW enable bits reset values. Tie each bit high to enable

 

 

Reset

read-modify-write for TCM interfaces at reset.c Use the

 

 

 

following values:

 

 

 

1: BTCM

 

 

 

0: ATCM

 

 

 

See Auxiliary Control Registers on page 4-38for more

 

 

 

information.

 

 

 

 

SLBTCMSB

Input

Tie-off

Use most significant bit of BTCM address to select B1TCM if

 

 

 

this signal is HIGH.

 

 

 

Use bit [3] of the BTCM address if this signal is LOW.

a.If the BTCM is configured with ECC, bit[2] and bit[1] must be the same value.

b.Not used if 32-bit ECC is included.

c.Not available in r0px revisions of the processor.

ARM DDI 0363E

Copyright © 2009 ARM Limited. All rights reserved.

A-6

ID013010

Non-Confidential, Unrestricted Access

 

Page 419
Image 419
ARM r1p3, R4F manual RMWENRAM10b