Level Two Interface

Dirty RAM access

The following tables show the data format for accessing the dirty RAM:

Table 9-42shows the format when parity is implemented, or no error scheme is implemented

Table 9-43shows the format when ECC is implemented.

Table 9-42 Dirty register format, with parity or with no error scheme

Data bit

Description

 

 

[63:27]

Not used, read-as-zero

 

 

[26:25]

Outer attributes, way 3

 

 

[24]

Dirty value, way 3

 

 

[23:19]

Not used, read-as-zero

 

 

[18:17]

Outer attributes, way 2

 

 

[16]

Dirty value, way 2

 

 

[15:11]

Not used, read-as-zero

 

 

[10:9]

Outer attributes, way 1

 

 

[8]

Dirty value, way 1

 

 

[7:3]

Not used, read-as-zero

 

 

[2:1]

Outer attributes, way 0

 

 

[0]

Dirty value, way 0

 

 

Note

When parity checking is enabled, all Cacheable accesses are forced to write-through. Therefore the dirty RAM is not used and does not require parity protection.

Table 9-43 Dirty register format, with ECC

Data bit

Description

 

 

[63:31]

Not used, read-as-zero

 

 

[30:27]

ECC, way 3

 

 

[26:25]

Outer attributes, way 3

 

 

[24]

Dirty value, way 3

 

 

[23]

Not used, read-as-zero

 

 

[22:19]

ECC, way 2

 

 

[18:17]

Outer attributes, way 2

 

 

[16]

Dirty value, way 2

 

 

[15]

Not used, read-as-zero

ARM DDI 0363E

Copyright © 2009 ARM Limited. All rights reserved.

9-31

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ARM R4F, r1p3 manual Dirty RAM access, Dirty register format, with ECC Data bit Description