ARM r1p3, R4F manual See also Burst, See also Beat

Glossary

Base register write-back

	Updating the contents of the base register used in an instruction target address calculation so that
	the modified address is changed to the next higher or lower sequential address in memory. This
	means that it is not necessary to fetch the target address for successive instruction transfers and
	enables faster burst accesses to sequential memory.
Beat	Alternative word for an individual transfer within a burst. For example, an INCR4 burst
	comprises four beats.
	See also Burst.
BE-8	Big-endian view of memory in a byte-invariant system.
	See also BE-32, LE, Byte-invariant and Word-invariant.
BE-32	Big-endian view of memory in a word-invariant system.
	See also BE-8, LE, Byte-invariant and Word-invariant.
Big-endian	Byte ordering scheme in which bytes of decreasing significance in a data word are stored at
	increasing addresses in memory.
	See also Little-endian and Endianness.
Big-endian memory	Memory in which:- a byte or halfword at a word-aligned address is the most significant byte or
	halfword within the word at that address - a byte at a halfword-aligned address is the most
	significant byte within the halfword at that address.
	See also Little-endian memory.
Block address	An address that comprises a tag, an index, and a word field. The tag bits identify the way that
	contains the matching cache entry for a cache hit. The index bits identify the set being
	addressed. The word field contains the word address that can be used to identify specific words,
	halfwords, or bytes within the cache entry.
	See also Cache terminology diagram on the last page of this glossary.
Branch prediction	The process of predicting if conditional branches are to be taken or not in pipelined processors.
	Successfully predicting if branches are to be taken enables the processor to prefetch the
	instructions following a branch before the condition is fully resolved. Branch prediction can be
	done in software or by using custom hardware. Branch prediction techniques are categorized as
	static, in which the prediction decision is decided before run time, and dynamic, in which the
	prediction decision can change during program execution.
Breakpoint	A breakpoint is a mechanism provided by debuggers to identify an instruction at which program
	execution is to be halted. Breakpoints are inserted by the programmer to enable inspection of
	register contents, memory locations, variable values at fixed points in the program execution to
	test that the program is operating correctly. Breakpoints are removed after the program is
	successfully tested.
	See also Watchpoint.
Burst	A group of transfers to consecutive addresses. Because the addresses are consecutive, there is
	no requirement to supply an address for any of the transfers after the first one. This increases
	the speed at which the group of transfers can occur. Bursts over AHB or AXI buses are
	controlled using the xBURST signals to specify if transfers are single, four-beat, eight-beat, or
	16-beat bursts, and to specify how the addresses are incremented.
	See also Beat.
Byte	An 8-bit data item.

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