ARM R4F, r1p3 manual Output ports timing parameters

AC Characteristics

Table 15-9 TCM interface input ports timing parameters (continued)

Input delay	Input
	delay	Signal name
minimum
	maximum
Clock uncertainty	50%	B1TCWAIT
Clock uncertainty	40%	B1TCLATEERROR
Clock uncertainty	50%	B1TCRETRY

The timing parameters for the dual-redundant core compare logic input control buses, DCCMINP[7:0] and DCCMINP2[7:0], are implementation-defined. Contact the implementer of the macrocell you are working with.

15.2.2Output ports timing parameters

Most output ports have a maximum output delay of 60%, that is the SoC is enabled to use 60% of the clock cycle.

Table 15-10shows the timing parameter for the miscellaneous output port.

Table 15-10 Miscellaneous output port timing parameter

Output delay	Output delay	Signal name
minimum	maximum
Clock uncertainty	10%	STANDBYWFI

Table 15-11shows the timing parameters for the interrupt output ports.

Table 15-11 Interrupt output ports timing parameters

Output delay	Output delay	Signal name
minimum	maximum
Clock uncertainty	60%	IRQACK
Clock uncertainty	60%	nPMUIRQ

Table 15-12shows the timing parameters for the AXI master output port.

Table 15-12 AXI master output port timing parameters

Output delay	Output delay	Signal name
minimum	maximum
Clock uncertainty	60%	AWIDM[3:0]
Clock uncertainty	60%	AWADDRM[31:0]
Clock uncertainty	60%	AWLENM[3:0]
Clock uncertainty	60%	AWSIZEM[2:0]
Clock uncertainty	60%	AWBURSTM[1:0]
Clock uncertainty	60%	AWLOCKM[1:0]
Clock uncertainty	60%	AWCACHEM[3:0]

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