ARM R4F, r1p3 manual Caches, 5 TCM, Preloading TCMs

Processor Initialization, Resets, and Clocking

•enable the FPU by setting the EN-bit in the FPEXC register, see Floating-Point Exception Register, FPEXC on page 12-7.

Note

Floating-point logic is only available with the Cortex-R4F processor.

3.1.4Caches

If the processor has been built with instruction or data caches, these must be invalidated before they are enabled, otherwise UNPREDICTABLE behavior can occur. See Cache operations on page 4-54.

If you are using an error checking scheme in the cache, you must enable this by programming the auxiliary control register as described in Auxiliary Control Registers on page 4-38before invalidating the cache, to ensure that the correct error code or parity bits are calculated when the cache is invalidated. An invalidate all operation never reports any ECC or parity errors.

3.1.5TCM

The processor does not initialize the TCM RAMs. It is not essential to initialize all the memory attached to the TCM interface but ARM recommends that you do. In addition, you might want to preload instructions or data into the TCM for the main application to use. This section describes various ways that you can perform data preloading. You can also configure the processor to use the TCMs from reset.

Preloading TCMs

You can write data to the TCMs using either store instructions or the AXI slave interface.

Depending on the method you choose, you might require:

•particular hardware on the SoC that you are using

•boot code

•a debugger connected to the processor.

Methods to preload TCMs include:

Memory copy with running boot code

The boot code includes a memory copy routine that reads data from a ROM, and writes it into the appropriate TCM. You must enable the TCM to do this, and it might be necessary to give the TCM one base address while the copy is occurring, and a different base address when the application is being run.

Copy data from the debug communications channel

The boot code includes a routine to read data from the Debug Communications Channel (DCC) and write it into the TCM. The debug host feeds the data for this operation into the DCC by writing to the appropriate registers on the processor APB debug port.

Execute code in debug halt state

The processor is put into debug halt state by the debug host, which then feeds instructions into the processor through the Instruction Transfer Register (ITR). The processor executes these instructions, which replace the boot code in either of the two methods described above.

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