Synchronization instructions, Clrex

Cycle Timings and Interlock Behavior

14.15 Synchronization instructions

This section describes the cycle timing behavior for the CLREX, DMB, DSB, ISB, LDREX, LDREXB,

LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, and SWPB instructions

In all cases the base register, Rn, is a Very Early Reg. Table 14-20shows the synchronization instructions cycle timing behavior.

Table 14-20 Synchronization instructions cycle timing behavior

Instruction	Cycles	Memory cycles	Result latency

CLREX	1	-	-

LDREX <Rt>, [Rn]	1	1	2

LDREXB <Rt>, [Rn]	1	1	2

LDREXH <Rt>, [Rn]	1	1	2

LDREXD <Rt>, [Rn]a	1	1	2
STREX <Rd>, <Rt>, [Rn]	1	1	2

STREXB <Rd>, <Rt>, [Rn]	1	1	2

STREXH <Rd>, <Rt>, [Rn]	1	1	2

STREXD <Rd>, <Rt>, <Rt2>, [Rn]a	1	1	2
SWP <Rt>, <Rt2>, [Rn]	2	2	3

SWPB <Rt>, <Rt2>, [Rn]	2	2	3

a. Address must be 64-bit aligned.

The synchronization instructions DMB, DSB, and ISB stall the pipeline for a variable number of cycles, depending on the current state of the memory system.

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ARM r1p3, R4F manual Synchronization instructions, Clrex

Contents

Cortex-R4 and Cortex-R4F Copyright 2009 ARM Limited. All rights reserved Cortex-R4 and Cortex-R4FTechnical Reference Manual Chapter Introduction Cortex-R4 and Cortex-R4F Technical Reference Manual Chapter Processor Initialization, Resets, and Clocking Chapter AC Characteristics Appendix B ECC Schemes List of Tables Adfsr and Aifsr bit functions Dirty register format, with ECC 11-12 Example interlocks 14-11 Table A-18 FPU signals Table C-1 List of Figures Cache operations C7 format for Set and Way Vector Catch Register format 11-20 Feedback on Preface About this book Using this bookProduct revision status Identifies the major revision of the product Typographical Conventions Signals Timing diagrams This section lists publications by ARM and by third parties Further readingARM publications Other publications ARM welcomes feedback on this product and its documentation FeedbackFeedback on this product Feedback on this book Introduction About the processor About the architecture This section describes the main components of the processor Components of the processorDebug on System control coprocessor on Interrupt handling on Floating Point Unit Data Processing UnitLoad/store unit Prefetch unit TCM interfaces Instruction and data cachesMemory Protection Unit 5 L2 AXI interfaces Error correction and detectionAXI master interface AXI slave interface System performance monitoring DebugETM interface Real-time debug facilities Interrupt handling System control coprocessorVIC port Low interrupt latency Changes Return from exception using data from the stack External interfaces of the processor Processor has the following interfaces for external accessAPB Debug interface ETM interface Test interface APB Debug interface Run mode Power managementStandby mode Shutdown mode Atcm Configurable optionsConfigurable options VFP BtcmFPU includeda MPU Atcmpcen Configurable options at reset Feature Options RegisterB0TCMPCEN B1TCMPCEN B0TCMECEN AtcmecenB1TCMECEN Atcmrmw Instruction decode Execution pipeline stagesNames of the pipeline stages and their functions are Iss First stage of data memory accessExecute stages Write-back of data from the execution pipelines Redundant core comparison Test features Design flow Product documentation, design flow, and architectureDocumentation Configuration inputs Build configurationSoftware configuration Architectural information Advanced Microcontroller Bus Architecture protocol Processor identification Product revision information Revision field, Main ID Register Variant field, Main ID RegisterVariant field, Debug ID Register Revision field, Debug ID Register Registers on Programmer’s ModelProgram status registers on Exceptions on About the programmer’s model Instruction set states Switching stateARM state Thumb state Operating modes Data types Byte-invariantbig-endian format Little-endian format Memory formatsByte-invariant big-endian format Little-endian format Register set Registers Register mode identifiers Mode Mode identifier General registers and program counter N, Z, C, and V bits Program status registers IT bits Q bit GE bits J bitDNM bits A bit E bitI and F bits Non-maskable fast interrupts on M40 Mode Visible state registers Thumb PSR mode bit valuesM bits Modification of PSR bits by MSR instructions ARM DDI 0363E Exceptions Reset on Interrupts on Aborts onException entry and exit summary Exception entry and exit summary Leaving an exception Taking an exception Interrupt request ResetInterrupts Non-maskable fast interrupts Fast interrupt requestProgram status registers on Non-maskable fast interrupts Interrupt controller Interrupt entry flowchart Interrupt entry sequence Prefetch aborts AbortsData aborts Precise aborts Aborts in Strongly Ordered and Device memory Imprecise aborts Supervisor call instruction Abort handler Breakpoint instruction Undefined instruction Exception vectors Acceleration of execution environments Architecture Reference Manual Unaligned and mixed-endian data access support Big-endian instruction support Resets on Processor Initialization, Resets, and ClockingReset modes on Initialization on Caches on TCM on Initialization1 MPU 2 CRS Preloading TCMs Caches5 TCM Preloading TCMs with parity or ECC DMA into TCMWrite to TCM directly from debugger Using TCMs from reset NRESET ResetsPRESETDBGn NSYSPORESET Power-on reset Reset modes Halt operation Processor resetNormal operation AXI interface clocking Clock gating ClockingAXI interface clocking Clock gating System Control Coprocessor System control coprocessor functional groups About the system control coprocessor Fcse PID System control coprocessor register functionsFunction Register/operation Reference to description Configuration Region System control and configurationTCM control TCM Status System performance Performance monitoring Cache control and configuration MPU control and configuration System performance monitor TCM control and configuration System performance monitor registers System validation ARM DDI 0363E RAZ System control coprocessor registersRegister allocation Undefined MPU Region Size Read/write Enable Undefined MPU Region Access Read/writeControl Undefined MPU Memory Region Read/write Number ARM DDI 0363E Count Undefined Undefined C3-c11 C12 Performance Monitor Read/writeEvent Select Read/write Unpredictable Performance Monitor Undefined C1-c15 C12 C0-c15 C13 C14 User Enable Read/writeRAZ,ignore Writes Context ID Read/write 7shows the arrangement of bits in the register 2 c0, Main ID Register Bits Field Function 3 c0, Cache Type RegisterMain ID Register bit functions 4 c0, TCM Type Register To access the Cache Type Register, read CP15 withCache Type Register bit functions Bits Field Function TCM Type Register bit functions Bits Field Function To access the MPU Type Register, read CP15 with To access the TCM Type Register, read CP15 with5 c0, MPU Type Register TCM Type Register bit functions 6 c0, Multiprocessor ID Register Processor Feature RegistersC0, Processor Feature Register 0, PFR0 C0, Processor Feature Register 1, PFR1 To access the Processor Feature Register 0 read CP15 withProcessor Feature Register 0 bit functions Processor Feature Register 1 bit functions 8 c0, Debug Feature Register To access the Processor Feature Register 1 read CP15 withDebug Feature Register 0 bit functions 3124 Reserved 9 c0, Auxiliary Feature Register To access the Debug Feature Register 0 read CP15 withMemory Model Feature Registers C0, Memory Model Feature Register 0, MMFR0 10 Memory Model Feature Register 0 bit functions C0, Memory Model Feature Register 1, MMFR1 11 Memory Model Feature Register 1 bit functions 16 Memory Model Feature Register 1 format DMB C0, Memory Model Feature Register 2, MMFR2WFI 3112 Reserved C0, Memory Model Feature Register 3, MMFR313 Memory Model Feature Register 3 bit functions 14 Instruction Set Attributes Register 0 bit functions Instruction Set Attributes RegistersC0, Instruction Set Attributes Register 0, ISAR0 20 Instruction Set Attributes Register 1 format C0, Instruction Set Attributes Register 1, ISAR1 Indicates support for if then instructions C0, Instruction Set Attributes Register 2, ISAR2ITE Indicates support for PSR instructions 16 Instruction Set Attributes Register 2 bit functionsPSR Thumb instruction sets C0, Instruction Set Attributes Register 3, ISAR317 Instruction Set Attributes Register 3 bit functions 23 Instruction Set Attributes Register 4 format C0, Instruction Set Attributes Register 4, ISAR4 18 Instruction Set Attributes Register 4 bit functions C0, Instruction Set Attributes Registers12 c0, Current Cache Size Identification Register 8KB 4KB 3130 Reserved 13 c0, Current Cache Level ID Register 15 c1, System Control Register 14 c0, Cache Size Selection Register AFE 23 System Control Register bit functionsTRE Nmfi = data caching disabled. This is the reset value Enables L1 data cache= data caching enabled = strict alignment fault checking enabled 24 Auxiliary Control Register bit functions Auxiliary Control RegistersC1, Auxiliary Control Register Axiscuen AxiscenDilsm Deolp Dbwr RsdisDlfo Dnch C15, Secondary Auxiliary Control Register 25 Secondary Auxiliary Control Register bit functions IXC DoofmacsOFC UFC Primary input RMWENRAM1 defines the reset value 17 c1, Coprocessor Access RegisterPrimary input RMWENRAM0 defines the reset value Atcmecc All other encodings for these FSR bits are Reserved Fault Status and Address RegistersC5, Data Fault Status Register To use the Dfsr read or write CP15 with C5, Instruction Fault Status Register28 Data Fault Status Register bit functions C5, Auxiliary Fault Status Registers To access the Ifsr read or write CP15 withThere are two auxiliary fault status registers 29 Instruction Fault Status Register bit functions 30 Adfsr and Aifsr bit functions C6, Data Fault Address Register= Atcm = Btcm 19 c6, MPU memory region programming registers C6, Instruction Fault Address Register C6, MPU Region Base Address Registers C6, MPU Region Size and Enable Registers 32 Region Size Register bit functions C6, MPU Region Access Control Registers158 Sub-region disable TEX 33 MPU Region Access Control Register bit functions C6, MPU Memory Region Number Register 34 Access data permission bit encodingUNP 35 MPU Memory Region Number Register bit functions Point of Unification PoU Cache operationsPoint of Coherency PoC Set and Way format Invalidate and clean operations Address format 37shows the cache sizes and the resultant bit range for Set36 Functional bits of c7 for Set and Way 37 Widths of the set field for L1 cache sizes Size Set Data Memory Barrier operation Data Synchronization Barrier operation21 c9, Btcm Region Register 38 Functional bits of c7 for address format Bits Field 39 Btcm Region Register bit functions To access the Btcm Region Register, read or write CP15 with22 c9, Atcm Region Register 23 c9, TCM Selection Register To access the Atcm Region Register, read or write CP15 with24 c11, Slave Port Control Register 40 Atcm Region Register bit functions 26 c13, Context ID Register 25 c13, Fcse PID Register312 Reserved RAZ/UNP 27 c13, Thread and Process ID Registers Ccnt overflow IRQ request C15, nVAL IRQ Enable Set RegisterValidation Registers Ccnt overflow FIQ request C15, nVAL FIQ Enable Set Register Ccnt overflow reset request C15, nVAL Reset Enable Set RegisterC15, nVAL Debug Request Enable Set Register Ccnt overflow debug request C15, nVAL IRQ Enable Clear Register 48 nVAL IRQ Enable Clear Register format C15, nVAL FIQ Enable Clear Register 303 Reserved UNP or Sbzp C15, nVAL Reset Enable Clear Register 51 nVAL Debug Request Enable Clear Register format C15, nVAL Debug Request Enable Clear Register 50 nVAL Cache Size Override Register C15, nVAL Cache Size Override Register318 Reserved B0000 4kB B0001 8kB B0011 16kB B0111 32kB B1111 64kB 53 Correctable Fault Location Register cache Correctable Fault Location Register 52 Correctable Fault Location Register cache Build Options Registers To access the Build Options 1 Register, write CP15 withC15, Build Options 1 Register C15, Build Options 2 Register Noicache 55 Build Options 2 RegisterNodcache Atcmes Noie BtcmesNofpu Nompu Noharderrorcach To access the Build Options 2 Register, write CP15 withDcachees Axibusparity Prefetch Unit About the prefetch unit Disabling program flow prediction Branch prediction Incorrect predictions and correction Configuring the branch predictorBranch predictor Return stack Events and Performance Monitor About the events Bit position Update ValueEvent bus interface bit functions Event ETMEXTOUT1 ETMEXTOUT0 Instruction cache access Non-cacheable access on AXI master busBut with different attributes Dual issue case a branch Dual issue case B1, B2, F2 load/store, F2D TCM correctable ECC error reported by prefetch unit Yes TCM correctable ECC error reported by load/store unit Yes About the PMU Performance monitoring registers are described Performance monitoring registers1 c9, Performance Monitor Control Register 2shows how the bit values correspond with the Pmnc Register Pmnc Register bit functions 2 c9, Count Enable Set Register Cntens Register bit functions Bits Field Function To access the Cntens Register, read or write CP15 with3 c9, Count Enable Clear Register Cycle counter enable clear To access the Cntenc Register, read or write CP15 with4 c9, Overflow Flag Status Register Cntenc Register bit functions Bits Field Function 5 c9, Software Increment Register To access the Flag Register, read or write CP15 with5shows how the bit values correspond with the Flag Register 6 c9, Performance Counter Selection Register To access the Swincr Register, read or write CP15 withSwincr Register bit functions Bits Field Function 313 Reserved RAZ on reads, Sbzp on writes Increment Counter SEL 7 c9, Cycle Count Register8 c9, Event Selection Register EVTSELx Register bit functions To access the EVTSELx Register, read or write CP15 with Useren Register bit functions 10 c9, User Enable Register9 c9, Performance Monitor Count Registers 10 Intens Register bit functions Bits Field Function 11 c9, Interrupt Enable Set RegisterCcnt overflow interrupt enable 11 Intenc Register bit functions Bits Field Function 12 c9, Interrupt Enable Clear RegisterCcnt overflow interrupt enable bit To access the Intenc Register, read or write CP15 with Use of the event bus and counters Event bus interface Memory Protection Unit MPU faults onMPU software-accessible registers on True Default memory mapAbout the MPU Region base address Memory regionsRegion size Subregions Region attributes Region access permissionsOverlapping regions Region Example of using subregions Example of using regions that overlap TCM regions Background regions Memory types Using memory types ARM DDI 0363E TEX20, C, and B encodings Description Memory Type Shareable? Region attributes 1BB Cacheable memory policies Following code is an example of disabling the MPU On page 7-2shows the default memory mapMPU interaction with memory system Background fault Permission fault Alignment fault MPU faultsBackground fault Permission fault On page 4-5shows the CP15 registers that control the MPU MPU software-accessible registers Level One Memory System About the L1 memory system L1 memory system block diagram Parity About the error detection and correction schemesParity Bit ECC on Hard errors Error checking and correctionBit ECC Read-Modify-Write Correct-and-retry Error correctionCorrect inline Faults Fault handlingClasses of fault that can occur are MPU faults TCM external faults External faultsCache and TCM parity and ECC errors Debug events Fault status informationPrecise and imprecise aborts Abort exceptions Usage models Precise abort exceptionsImprecise abort exceptions AXI Correctable errorsTypes of aborts Conditions Source Precise Fatal ARM DDI 0363E TCM attributes and permissions About the TCMs Handling TCM parity errors on Handling TCM ECC errors on Atcm and Btcm configurationTCM internal error detection and correction TCM arbitration Handling TCM parity errorsHandling TCM ECC errors TCM port protocol External TCM errorsTCM initialization AXI slave interfaces for TCMs Store buffer About the caches Store buffer merging Cache maintenance operationsStore buffer behavior Store buffer draining Error build options Cache error detection and correction Cache parity error behavior Value Behavior Address decoder faultsHandling cache parity errors Cache ECC error behavior Value Behavior Handling cache ECC errors Errors on data cache read Errors on instruction cache readErrors on data cache write Errors on evictions Invalidate all instruction cache Clean data cache by set/way Tag RAM Cache RAM organizationDirty RAM on Data RAM on Tag RAM Data RAM Dirty RAMCache sizes and tag RAM organization Tag RAM organization Organization of a dirty RAM line Nonsequential read operation performed with one RAM access Data RAM sizes without parity or ECC implemented 13 Data cache RAM bits, with parity Description Disabling or enabling all of the caches Cache interaction with memory systemFollowing code is an example of enabling caches 15 Data cache data RAM sizes with ECC Cache size Data RAMs Disabling or enabling data cache Disabling or enabling error checkingDisabling or enabling instruction cache MCR p15 R0, c1 Write System Control Register Internal exclusive monitor Memory types and L1 memory system behavior TCM error events Error detection eventsInstruction-cache error events Data-cache error events ARM DDI 0363E Level Two Interface About the L2 interface Attribute Value Comments AXI master interface1shows the AXI master interface attributes Outstanding write/read access on different IDs Identifiers for AXI bus accessesOutstanding write accesses with the same ID Write response Memory attributes Eviction bufferArcachem and Awcachem encodings Encoding a Meaning Aruserm and Awuserm encodings Memory system implications for AXI accesses Linefills on AXI master interface transfersStrongly Ordered and Device transactions on Strongly Ordered and Device transactions Restrictions on AXI transfersNon-cacheable Ldrb Address20 Ldrh from Strongly Ordered or Device memory Address30 LDR or LDM that transfers one register LDM5, Strongly Ordered or Device memory Address40 LDM that transfers five registers Strh to Strongly Ordered or Device memory Address20 Strb to Strongly Ordered or Device memory Address40 First Wstrbm STR or STM of one registerSTM of seven registers Non-cacheable reads LinefillsCache line write-back eviction 15 LDR or LDM1 from Non-cacheable Normal memory Address20 14 Ldrh from Non-cacheable Normal memory Address20 Non-cacheable or write-through writes AXI transaction splitting 20 AXI transaction splitting, data in two cache lines Normal write merging Example 9-1 Write merging ARM DDI 0363E AXI slave interface for cache RAMs AXI slave interface AXI slave control TCM parity and ECC supportCache parity and ECC support 25 AXI slave interface attributes AXI slave characteristics Enabling or disabling AXI slave accesses 26 RAM region decode AxUSERS bit One-hot RAM select Accessing RAMs using the AXI slave interfaceTCM RAM access on Cache RAM access on ARADDRSMSB, see Table TCM RAM access27 TCM chip-select decode Btcm ports RAM selected This section contains the following Cache RAM accessMemory map when accessing the cache RAMs 0010 Bank 0100 1000 Data RAM access31 Cache data RAM bank/address decode Inputs ARADDRS1815 0001 Bank 0010 0100 1000 35 Data format, data cache, with ECC Data bit Description 34 Data format, instruction cache, with ECC Tag RAM access ARM DDI 0363E 43 Dirty register format, with ECC Data bit Description Dirty RAM access ARADDRS1815 = 4b1111 Other examples of accessing cache RAMs About power control on Power management on Power Control About power control Standby mode Run modeDormant mode Shutdown mode Communication to the Power Management Controller Debug state on Cache debug on Debug Debug host Protocol converter Debug target Debug systemsDebug host Protocol converter Halting debug-mode debugging About the debug unitMonitor debug-mode debugging Programming the debug unit All other state information associated with the debug unit Debug register interface 11.3.2 CP14 access permissionsCoprocessor registers Coprocessor registers summary Memory-mapped registers Offset Register Access Mnemonic Description Hex NumberInstruction Mnemonic Description Debug memory-mapped registers Memory addresses for breakpoints and watchpoints Effects of resets on debug registers Power domainsAPB port access permissions Privilege of memory access permission Lock External debug interface access permissions RegistersOther Debug registers Other registers Debug register descriptions Accessing debug registers6shows the CP14 debug register map 11.4.2 CP14 c0, Debug ID Register BRP Debug ID Register functionsWRP 11.4.3 CP14 c0, Debug ROM Address Register To use the Debug ID Register, read CP14 c0 withTo use the Debug ROM Address Register, read CP14 c0 with 11.4.4 CP14 c0, Debug Self Address Offset Register Debug Self Address Offset Register functions Debug Self Address Offset Register format 10 Debug Status and Control Register functions 11.4.5 CP14 c1, Debug Status and Control Register Flag is set to 1 on entry to debug state ARM Execute ARM instruction enable bit= disabled, this is the reset value MOE DTR access mode Data Transfer Register 12 Watchpoint Fault Address Register functions Watchpoint Fault Address RegisterVector Catch Register Reserved RAZ SVC Debug State Cache Control Register Bits Field Reset Description ValueInstruction Transfer Register 14 Debug State Cache Control Register functions 315 Reserved Debug Run Control Register15 Debug Run Control Register functions Breakpoint Control Registers Breakpoint Value Registers 17 Breakpoint Control Registers functions Corresponding instruction address breakpoint +0 is accessed18 Meaning of BVR bits BVR2220 Meaning 19 Watchpoint Value Registers functions Bits Description Watchpoint Value RegistersWatchpoint Control Registers 20 Watchpoint Control Registers functions 11 Watchpoint Control Registers format Operating System Lock Status Register Accessed 21 OS Lock Status Register functions Authentication Status Register Device Power-down and Reset Status Register Device Power-down and Reset Control Register= Dbgnopwrdwn is LOW. This is the reset value 23 Prcr functions 24 Prsr functions 15 Prsr format Processor ID Registers Management registers 27 Claim Tag Set Register functions Bits Field Function Claim RegistersClaim Tag Set Register 318 Reserved RAZ or Sbzp Claim tag clear Reset value is Lock Access RegisterClaim Tag Clear Register Lock Status Register 30 Device Type Register functions Device Type RegisterDebug Identification Registers Field Size Description 32 Fields in the Peripheral Identification Registers33 Peripheral ID Register 0 functions Bits Value Description 35 Peripheral ID Register 2 functions 34 Peripheral ID Register 1 functions36 Peripheral ID Register 3 functions 37 Peripheral ID Register 4 functions Component Identification Register 10201021 1022 Software debug event Debug events Behavior of the processor on debug events Halting debug eventDebug event priority Watchpoint debug events Debug exception Following sections describe 40shows the values in the link register after exceptionsEffect of debug exceptions on CP15 registers and Wfar Four CP15 registers that record abort information are Avoiding unrecoverable states Privilege on Debug stateEntering debug state 41 Read PC value after debug state entry 41 Read PC value after debug state entry Debug event Behavior of the PC and Cpsr in debug state Executing instructions in debug state Accessing registers and memoryWriting to the Cpsr in debug state Privilege Effect of debug state on non-invasive debug Coprocessor instructionsEffects of debug events on processor registers Exceptions in debug state Imprecise Data Abort Precise Data abortImprecise Data Aborts on entry and exit from debug state Leaving debug state Sets the DSCR1 core restarted flag to This section describes cache debug. It consists Cache debugCache pollution in debug state Cache coherency in debug state Miscellaneous debug signals APB signalsThis section describes the miscellaneous debug signals External debug interface Changing the authentication signals Authentication signals42 Authentication signal restrictions Dbgen a Non-invasive debug permitted Issue an Instruction Synchronization Barrier ISB instruction Example 11-1 Executing an ARM instruction through the ITR Using the debug functionality Debug communications channel Rules for accessing the DCC Debugger access to the DCC Software access to the DCCExample 11-5shows the code for host-to-target data transfer Example 11-4 Target to host data transfer host end This section describes the following operations Programming breakpoints and watchpointsProgramming simple breakpoints and the byte address select Example 11-6 Polling the DCC host end Example 11-7 Setting a simple breakpoint Setting a simple aligned watchpoint Example 11-8 Setting a simple aligned watchpoint Setting a simple unaligned watchpoint 45shows some examples Example 11-9 Setting a simple unaligned watchpointSingle-stepping Not required Example 11-11 Entering debug state Debug state entryExample 11-10 Single-stepping off an instruction Example 11-12 Leaving debug state Debug state exit This section describes the following Accessing registers and memory in debug stateReading and writing registers through the DCC Example 11-13 Reading an ARM register Example 11-15shows the code to read the PC Reading the PC in debug stateReading the Cpsr in debug state Example 11-16shows the code for reading the Cpsr Reading memory Example 11-19 Checking for an abort after memory accessExample 11-18shows the code for reading a byte of memory Example 11-17 Writing the Cpsr Example 11-21 Reading a word of memory Example 11-20 Reading a block of bytes of memory Example 11-23 Reading registers in stall mode Example 11-22 Changing the DTR access modeExample 11-24 Writing registers in stall mode Fast register read/write Example 11-25 Reading a block of words of memory Fast memory read/write Example 11-27 Reading a coprocessor register Accessing coprocessor registers 11-70 Debugging systems with energy management capabilities Emulating power down 11-72 FPU Programmer’s Model About the VFPv3-D16 architecture About the FPU programmer’s modelFPU functionality FPU views of the register bank General-purpose registers 1shows the VFP system registers in the Cortex-R4F FPU System registersVFPv3 architecture describes the following system registers Fpsid is privileged access only All hardware ID information is privileged access onlyMvfr registers are privileged access only This is a change in VFPv3 compared to VFPv2 Fpscr Register bit functions Floating-Point Status and Control Register, FpscrDNM Rmode LEN Floating-Point Exception Register, FpexcIDE RAZ DNM IXE RAZ UFE OFE DZE IOE IDC Floating-Point Exception Register bit functions Media and VFP Feature Registers, MVFR0 and MVFR1DEX MVFR0 Register bit functions Full denormal arithmetic supported for VFP MVFR1 Register bit functions Full-compliance mode Full-compliance mode Flush-to-zero mode Default NaN modeFlush-to-zero mode Default NaN mode Complete implementation of the Ieee 754 standard Compliance with the Ieee 754 standardIeee 754 standard implementation choices NaN handling Underflow ComparisonsQNaN and SNaN handling CDP Exceptions Integration Test Registers About Integration Test Registers Programming and reading Integration Test Registers Software access using APB Itetmif Register ItctrlItmiscout Itmiscin 1110 Processor integration testing1312 Performing integration testing Using the Integration Test Registers Itetmif Register bit assignments Bits Name Function Itetmif Register ETM interface Itmiscout Register bit assignments Bits Name Function Itmiscout Register Miscellaneous OutputsItmiscin Register Miscellaneous Inputs Bits Name Function Integration Mode Control Register ItctrlDbgrestart Etmextout 7shows the fields of the Itctrl Register Bits Access Reset value Name FunctionRAZ/SBZP Intmode Multiplies on Divide on Branches on Cycle Timings and Interlock Behavior Dual issue on Instruction execution overview About cycle timings and interlock behavior Flag-setting instructions Following sequence where R1 is a Late Reg takes two cyclesConditional instructions Definition of terms Assembler language syntax Instruction Behavior Sequence Register interlock examplesTakes two cycles because there are no register dependencies Takes three cycles because of the result latency of R1 Cycle counts if destination is the PC Data processing instructionsCycle counts if destination is not PC Register controlled shifts Example interlocksShifter QADD, QDADD, QSUB, and Qdsub instructions SEL Media data-processing Instruction sequence Behavior Sum of Absolute Differences SADResult of the USAD8 instruction USAD8 instruction Umlals Multiplies 14-13 Divide Example instruction Cycles Memory Comments Branches10 Branch instruction cycle timing behavior Processor state updating instructions Mode changingAll MRS instructions All MSR instructions to the Spsr 13shows the cycle timing behavior for loads to the PC Single load and store instructions Example instruction Cycles Memory Result Comments Latency Base register update13 Cycle timing behavior for loads to the PC 14-19 Load and Store Double instructions Register offset, then 3-issue cycles Write-back Load and Store Multiple instructions Correct condition prediction and correct Load Multiples, where the PC is in the register listReturn stack prediction Correct condition prediction and incorrect 14-23 RFE and SRS instructions Clrex Synchronization instructions Some instructions such as cache operations take more cycles Coprocessor instructions Prefetch Abort Undefined Instruction SVC formerly SWI Miscellaneous instructions Serializing Floating-point register transfer instructionsBlocking and serializing Bit aligned address Floating-point load/store instructionsNot aligned 2,2 4,5 2,3 Floating-point single-precision data processing instructions Floating-point double-precision data processing instructions Dual issue rules Dual issueDual issue rules Permitted combinations on 28 Permitted instruction combinations Dual issue First instruction Second instruction CasePermitted combinations Any single-precision CDPi, excluding Case F2stbMultiply-accumulate instructionso Case F2Db Processor timing on Processor timing parameters on AC Characteristics Processor timing Input port timing parameters Processor timing parametersClock uncertainty 10% Clock uncertainty 50% Clock uncertainty 60% 3shows the timing parameters for the interrupt input ports4shows the input timing parameters for the AXI master port Rreadys 5shows the input timing parameters for the AXI slave port 7shows the input timing parameters for the ETM input ports 6shows the input timing parameters for the debug input ports Clock uncertainty 40% 8shows the timing parameters for the test input portsClock uncertainty 65% 11shows the timing parameters for the interrupt output ports Output ports timing parameters Write response channel Clock uncertainty 60% 13shows the timing parameters for the AXI slave output ports BRESPS10 Clock uncertainty 45% 16shows the timing parameters for the test output ports Fpidc 18shows the timing parameters for the FPU output signals 15-13 FPU signals on page A-23 Processor Signal Descriptions From any clock About the processor signal descriptionsAny Signal Direction Clocking Description Global signalsTable A-1 Global signals Table A-2shows the processor configuration signals Configuration signalsTable A-2 Configuration signals Information Tie High for odd parity Tie LOW for even parity RMWENRAM10b Interrupt signals, including VIC interface signals AXI master port L2 interface signalsTable A-4 AXI master port signals for the L2 interface Identification tag for the write response signal Identification tag for the write data group of signalsIdentification tag for the read address group of signals Protection signals provide addition information about a bus Table A-5 AXI master port error detection signals AXI master port error detection signalsTable A-6 AXI slave port signals for the L2 interface AXI slave port AXI specification Protection information, privileged/normal access. AWPROT0Protection information, privileged/normal access. ARPROT0 One to 16. a four bit binary value minus one determines ATCM, one hot. AWUSERS30 signal is not part AXI slave port error detection signalsStandard AXI specification Table A-7 AXI slave port error detection signals Table A-9shows the B0TCM port signals TCM interface signalsTable A-8shows the Atcm port signals = DMA Table A-10shows the B1TCM port signalsTable A-10 B1TCM port signals Address for B1TCM data RAM B1TCM RAM access is sequentialWrite data for B1TCM data RAM Write parity or ECC code for B1TCM Table A-11 Dual core interface signals Dual core interface signalsTable A-11shows the dual redundant core interface signals Table A-12 Debug interface signals Debug interface signalsTable A-13shows the debug miscellaneous signals Input Tie-off Debug ROM physical address valid Table A-13 Debug miscellaneous signalsInput Tie-off Debug self-address offset Input Tie-off Debug self-address offset valid Table A-14 ETM interface signals ETM interface signalsTable A-14shows the ETM interface signals Table A-15 Test signals Test signalsTable A-15shows the test signals Table A-16shows the Mbist signals Mbist signals Table A-17shows the validation signals Validation signals Table A-18 FPU signals FPU signals ECC scheme selection guidelines on page B-2 ECC Schemes ECC scheme selection guidelines Revisions NCPUHALT removed from timing diagram Added sectionsClarified byte-invariant big-endian format Clarified little-endian format Change Location Table C-1 Differences between issue B and issue C No technical changes Table C-2 Differences between issue C and issue D Abort, and an internal or External Abort GlossarySee also Data Abort, External Abort and Prefetch Abort Base register write-back See Advanced High-performance Bus See also Advanced High-performance BusThat are divisible by four and two respectively See Advanced Microcontroller Bus Architecture Active transfer Active read transactionActive write transaction Completed transfer Read issuing capability Read ID widthWrite ID capability Write ID width See also Beat See also Burst Accessed in parallel during a cache look-up Accesses are expected to be word-alignedSee also Word-invariant Bus See also Dirty See also Clean See Embedded Trace Macrocell By individual implementations An instruction that is architecturally UndefinedOption chosen does not affect software compatibility Precision and the fraction is all zeros See also Halt mode Serviced while normal program execution is suspendedSee Cold reset Result of attempting to access invalid instruction memory See Should Be One Or equal to 1 and is not restricted to being a power of twoSee Should Be Zero See Boundary scan chain Increment of +2 See Debug test access portDestination precision User trap handler is executed Bit for the exception is set Expected behavior for an unaligned accessProcessor-specific. a victim is also known as a cast out A processor Cache terminology diagram