ARM r1p3, R4F manual ETMEXTOUT0, ETMEXTOUT1

		Events and Performance Monitor
		Table 6-1 Event bus interface bit functions (continued)
	EVNTBUS	Description	CFLR	Event
				Ref.
	bit position		update
				Value
[8]		Exception return architecturally executed.	-	0x0A
		This event occurs on every exception return, for example, RFE, MOVS PC, LDM
		PC^.
[9]		Change to Context ID executed.	-	0x0B
[10]		Software change of PC, except by an exception, architecturally executed.	-	0x0C
[11]		B immediate, BL immediate or BLX immediate instruction architecturally	-	0x0D
		executed (taken or not taken).
[12]		Procedure return architecturally executed, other than exception returns, for	-	0x0E
		example, BX Rm; LDM PC.
		MOV PC, LR does not generate this event, because it is not predicted as a return.
[13]		Unaligned access architecturally executed.	-	0x0F
		This event occurs for each instruction that was to an unaligned address that
		either triggered an alignment fault, or would have done so if the System
		Control Register A-bit had been set.
[14]		Branch mispredicted or not predicted.	-	0x10
		This event occurs for every pipeline flush caused by a branch.
	N/A	Cycle count.	-	0x11
[15]		Branches or other change in program flow that could have been predicted by	-	0x12
		the branch prediction resources of the processor.
[16]		Stall because instruction buffer cannot deliver an instruction.	-	0x40
		This can indicate an ICache miss. This event occurs every cycle where the
		condition is present.
[17]		Stall because of a data dependency between instructions.	-	0x41
		This event occurs every cycle where the condition is present.
[18]		Data cache write-back.	-	0x42
		This event occurs once for each line that is written back from the cache.
[19]		External memory request.	-	0x43
		Examples of this are cache refill, Non-cacheable accesses, write-through
		writes, cache line evictions (write-back).
[20]		Stall because of LSU being busy.	-	0x44
		This event takes place each clock cycle where the condition is met. A high
		incidence of this event indicates the pipeline is often waiting for transactions
		to complete on the external bus.
[21]		Store buffer was forced to drain completely.	-	0x45
		Examples of this are DMB, Strongly Ordered memory access, or similar events.
	N/A	The number of cycles FIQ interrupts are disabled.	-	0x46
	N/A	The number of cycles IRQ interrupts are disabled.	-	0x47
	N/A	ETMEXTOUT[0].	-	0x48
	N/A	ETMEXTOUT[1].	-	0x49
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