ARM r1p3, R4, R4F

Introduction

ID013010 Non-Confidential, Unrestricted Access

• 512KB

•1MB

•2MB

•4MB

•8MB.

The TCMs are external to the processor. This provides flexibility in optimizing the TCM

subsystem for performance, power, and RAM type. The INITRAMA and INITRAMB pins

enable booting from the ATCM or BTCM, respectively. Both the ATCM and BTCM support

wait states.

For more information, see Chapter 8 Level One Memory System.

Error correction and detection

To increase the tolerance of the system to soft memory faults, you can configure the caches for

either:

• parity generation and error correction/detection

• ECC code generation, single-bit error correction, and two-bit error detection.

Similarly, you can configure the TCM interfaces for:

• parity generation and error detection

• ECC code generation, single-bit error correction, and two-bit error detection.

For more information, see Chapter 8 Level One Memory System.

1.3.5 L2 AXI interfaces

The L2 AXI interfaces enable the L1 memory system to have access to peripherals and to

external memory using an AXI master and AXI slave port.

AXI master interface

The AXI master interface provides a high bandwidth interface to second level caches, on-chip

RAM, peripherals, and interfaces to external memory. It consists of a single AXI port with a

64-bit read channel and a 64-bit write channel for instruction and data fetches.

The AXI master can run at the same frequency as the processor, or at a lower synchronous

frequency. If asynchronous clocking is required an external asynchronous AXI slice is required.

AXI slave interface

The AXI slave interface enables AXI masters, including the AXI master port of the processor,

to access data and instruction cache RAMs and TCMs on the AXI system bus. You can use this

for DMA into and out of the TCM RAMs and for software test of the TCM and cache RAMs.

The slave interface can run at the same frequency as the processor or at a lower, synchronous

frequency. If asynchronous clocking is required an external asynchronous AXI slice is required.

Bits in the Auxiliary Control Register and Slave Port Control Register can control access to the

AXI slave. Access to the TCM RAMs can be granted to any master, to only privileged masters,

or completely disabled. Access to the cache RAMs can be separately controlled in a similar way.