Cycle Timings and Interlock Behavior

14.22 Floating-point double-precision data processing instructions

This section describes the cycle timing behavior for all double-precision VFP CDP instructions. This includes arithmetic instructions such as VMUL.F64, data and immediate moving instructions such as “VMOV.F64 <Dd>, #<imm>”, VABS.F64, VNEG.F64, and “VMOV <Dd>, <Dm>”, and comparison instructions and conversion instructions.

Table 14-27shows the floating-point double-precision data processing instructions cycle timing behavior

Table 14-27 Floating-point double-precision data processing instructions cycle timing behavior

Example instruction

Cycles

Early Reg

Result latency

 

 

 

 

VMLA.F64 <Dd>, <Dn>, <Dm>a

13

<Dn>, <Dm>

19

VADD.F64 <Dd>, <Dn>, <Dm>b

3

<Dn>, <Dm>

9

VDIV.F64 <Dd>, <Dn>, <Dm>

3

<Dn>, <Dm>

96

 

 

 

 

VSQRT.F64 <Dd>, <Dm>

3

<Dm>

96

 

 

 

 

VMOV.F64 <Dd>, #<imm>

1

-

1

 

 

 

 

VMOV.F64 <Dd>, <Dm>c

1

-

1

VCMP.F64 <Dd>, <Dm>d

2

<Dd>, <Dm>

-

VCMPE.F64 <Dd>, #0.0d

2

<Dm>

-

VCVT.F64.U32 <Dd>, <Sm>e

3

<Dm>

7

VCVT.F64.U32 <Dd>, <Dd>, #<fbits>f

3

<Dd>

7

VCVTR.U32.F64 <Sd>, <Dm>g

3

<Dm>

7

VCVT.U32.F64 <Dd>, <Dd>, #<fbits>h

3

<Dd>

7

VCVT.F32.F64 <Sd>, <Dn>

3

<Dm>

7

a.Also VMLS.F64, VNMLS.F64, and VNMLA.F64.

b.Also VSUB.F64, VMUL.F64, and VNMUL.F64.

c.Also VABS.F64 and VNEG.F64.

d.Also VCMPE.F64.

e.Also VCVT.F64.S32.

f.Also VCVT.F64.U16, VCVT.F64.S32, and VCVT.F64.S16.

g.Also VCVT.U32.F64, VCVTR.S32.F64, and VCVT.S32.F64.

h.Also VCVT.U16.F64, VCVT.S32.F64, and VCVT.S16.F64.

ARM DDI 0363E

Copyright © 2009 ARM Limited. All rights reserved.

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ARM R4F, r1p3 manual Floating-point double-precision data processing instructions