Load and Store Double instructions | ARM R4F, r1p3 guide

Cycle Timings and Interlock Behavior

14.12 Load and Store Double instructions

This section describes the cycle timing behavior for the LDRD and STRD instructions.

The LDRD and STRD instructions:

•Are normally single-cycle issue. Both the base and any offset register are Very Early Regs.

•Are 3-cycle issue if offset or pre-increment addressing with a negative register offset is used. Both the base and any offset register are Very Early Regs.

•Take only one memory cycle if the address is doubleword aligned.

•Take two memory cycles if the address is not doubleword aligned.

Table 14-15shows the cycle timing behavior for LDRD and STRD instructions.

Table 14-15 Load and Store Double instructions cycle timing behavior

				Cycles with	Memory	Result	Result latency
	Example instruction		Cycles	Cycles with	Memory	latency	Result latency
	Example instruction		Cycles	base writeback	cycles	latency	(base register)
				base writeback	cycles	(LDRD)	(base register)
						(LDRD)

	Address is doubleword aligned
		LDRD R0, R1, <addr_md_1cycle>a	1	2	1	2, 2	2
		LDRD R0, R1, <addr_md_3cycle>a	3	4	1	4, 4	4
	Address not doubleword aligned
		LDRD R0, R1, <addr_md_1cycle>a	2	2	2	2, 3	2
		LDRD R0, R1, <addr_md_3cycle>a	4	4	2	4, 5	4

a. See Table 14-16 for an explanation of <addr_md_1cycle> and <addr_md_3cycle>.

Table 14-16shows the explanation of <addr_md_1cycle> and <addr_md_3cycle> used in

Table 14-15.

Table 14-16 <addr_md_1cycle> and <addr_md_3cycle> LDRD example instruction explanation

Example instruction

Very Early Reg Comments

<addr_md_1cycle>
	LDRD <Rt>, <Rt2>, [<Rn>,		#<imm>]	(!)	<Rn>

	LDRD	<Rt>, <Rt2>, [<Rn>,	<Rm>] (!)		<Rn>, <Rm>

	LDRD	<Rt>, <Rt2>, [<Rn>], #<imm>			<Rn>

If post-increment addressing, pre-increment addressing with an immediate offset or a positive register offset, then 1-issue cycle

LDRD	<Rt>, <Rt2>, [<Rn>], +/-<Rm>	<Rn>, <Rm>

<addr_md_3cycle>
LDRD	<Rt>, <Rt2>, [<Rn>, -<Rm>] (!)	<Rn>,<Rm>	If pre-increment addressing with a negative
			register offset, then 3-issue cycles

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ARM R4F, r1p3 manual Load and Store Double instructions, Register offset, then 3-issue cycles

Contents

Cortex-R4 and Cortex-R4F Cortex-R4 and Cortex-R4F Technical Reference ManualCopyright 2009 ARM Limited. All rights reserved Cortex-R4 and Cortex-R4F Technical Reference Manual Chapter Introduction Chapter Processor Initialization, Resets, and Clocking Chapter AC Characteristics Appendix B ECC Schemes List of Tables Adfsr and Aifsr bit functions Dirty register format, with ECC 11-12 Example interlocks 14-11 Table A-18 FPU signals Table C-1 List of Figures Cache operations C7 format for Set and Way Vector Catch Register format 11-20 Preface Feedback on Using this book About this bookProduct revision status Identifies the major revision of the product Conventions Typographical Timing diagrams Signals Further reading This section lists publications by ARM and by third partiesARM publications Other publications Feedback ARM welcomes feedback on this product and its documentationFeedback on this product Feedback on this book Introduction About the processor About the architecture Components of the processor This section describes the main components of the processorDebug on System control coprocessor on Interrupt handling on Data Processing Unit Floating Point UnitLoad/store unit Prefetch unit Instruction and data caches Memory Protection UnitTCM interfaces Error correction and detection 5 L2 AXI interfacesAXI master interface AXI slave interface Debug System performance monitoringETM interface Real-time debug facilities System control coprocessor Interrupt handlingVIC port Low interrupt latency Return from exception using data from the stack Changes Processor has the following interfaces for external access External interfaces of the processorAPB Debug interface ETM interface Test interface APB Debug interface Power management Run modeStandby mode Shutdown mode Configurable options Configurable optionsAtcm Btcm VFPFPU includeda MPU Configurable options at reset Feature Options Register AtcmpcenB0TCMPCEN B1TCMPCEN Atcmecen B0TCMECENB1TCMECEN Atcmrmw Execution pipeline stages Names of the pipeline stages and their functions areInstruction decode First stage of data memory access IssExecute stages Write-back of data from the execution pipelines Redundant core comparison Test features Product documentation, design flow, and architecture DocumentationDesign flow Build configuration Configuration inputsSoftware configuration Architectural information Advanced Microcontroller Bus Architecture protocol Product revision information Processor identification Variant field, Main ID Register Revision field, Main ID RegisterVariant field, Debug ID Register Revision field, Debug ID Register Programmer’s Model Registers onProgram status registers on Exceptions on About the programmer’s model Switching state Instruction set statesARM state Thumb state Operating modes Data types Memory formats Byte-invariantbig-endian format Little-endian formatByte-invariant big-endian format Little-endian format Registers Register set Register mode identifiers Mode Mode identifier General registers and program counter Program status registers N, Z, C, and V bits Q bit IT bits J bit DNM bitsGE bits E bit A bitI and F bits Non-maskable fast interrupts on PSR mode bit values M40 Mode Visible state registers ThumbM bits Modification of PSR bits by MSR instructions ARM DDI 0363E Reset on Interrupts on Aborts on ExceptionsException entry and exit summary Exception entry and exit summary Taking an exception Leaving an exception Reset InterruptsInterrupt request Fast interrupt request Program status registers on Non-maskable fast interruptsNon-maskable fast interrupts Interrupt entry flowchart Interrupt controller Interrupt entry sequence Aborts Prefetch abortsData aborts Precise aborts Imprecise aborts Aborts in Strongly Ordered and Device memory Abort handler Supervisor call instruction Undefined instruction Breakpoint instruction Exception vectors Acceleration of execution environments Unaligned and mixed-endian data access support Architecture Reference Manual Big-endian instruction support Processor Initialization, Resets, and Clocking Resets onReset modes on Initialization on Initialization Caches on TCM on1 MPU 2 CRS Caches 5 TCMPreloading TCMs DMA into TCM Write to TCM directly from debuggerPreloading TCMs with parity or ECC Using TCMs from reset Resets NRESETPRESETDBGn NSYSPORESET Reset modes Power-on reset Processor reset Normal operationHalt operation Clocking AXI interface clocking Clock gatingAXI interface clocking Clock gating System Control Coprocessor About the system control coprocessor System control coprocessor functional groups System control coprocessor register functions Function Register/operation Reference to descriptionFcse PID System control and configuration Configuration RegionTCM control TCM Status System performance Performance monitoring MPU control and configuration Cache control and configuration TCM control and configuration System performance monitor System validation System performance monitor registers ARM DDI 0363E System control coprocessor registers Register allocationRAZ Enable Undefined MPU Region Access Read/write Undefined MPU Region Size Read/writeControl Undefined MPU Memory Region Read/write Number ARM DDI 0363E Undefined C3-c11 C12 Performance Monitor Read/write Event Select Read/write Unpredictable Performance MonitorCount Undefined C14 User Enable Read/write Undefined C1-c15 C12 C0-c15 C13RAZ,ignore Writes Context ID Read/write 2 c0, Main ID Register 7shows the arrangement of bits in the register 3 c0, Cache Type Register Main ID Register bit functionsBits Field Function To access the Cache Type Register, read CP15 with 4 c0, TCM Type RegisterCache Type Register bit functions Bits Field Function TCM Type Register bit functions Bits Field Function To access the TCM Type Register, read CP15 with To access the MPU Type Register, read CP15 with5 c0, MPU Type Register TCM Type Register bit functions Processor Feature Registers C0, Processor Feature Register 0, PFR06 c0, Multiprocessor ID Register To access the Processor Feature Register 0 read CP15 with C0, Processor Feature Register 1, PFR1Processor Feature Register 0 bit functions Processor Feature Register 1 bit functions To access the Processor Feature Register 1 read CP15 with 8 c0, Debug Feature RegisterDebug Feature Register 0 bit functions 3124 Reserved To access the Debug Feature Register 0 read CP15 with 9 c0, Auxiliary Feature RegisterMemory Model Feature Registers C0, Memory Model Feature Register 0, MMFR0 C0, Memory Model Feature Register 1, MMFR1 10 Memory Model Feature Register 0 bit functions 16 Memory Model Feature Register 1 format 11 Memory Model Feature Register 1 bit functions C0, Memory Model Feature Register 2, MMFR2 WFIDMB C0, Memory Model Feature Register 3, MMFR3 13 Memory Model Feature Register 3 bit functions3112 Reserved Instruction Set Attributes Registers C0, Instruction Set Attributes Register 0, ISAR014 Instruction Set Attributes Register 0 bit functions C0, Instruction Set Attributes Register 1, ISAR1 20 Instruction Set Attributes Register 1 format C0, Instruction Set Attributes Register 2, ISAR2 ITEIndicates support for if then instructions 16 Instruction Set Attributes Register 2 bit functions PSRIndicates support for PSR instructions C0, Instruction Set Attributes Register 3, ISAR3 17 Instruction Set Attributes Register 3 bit functionsThumb instruction sets C0, Instruction Set Attributes Register 4, ISAR4 23 Instruction Set Attributes Register 4 format C0, Instruction Set Attributes Registers 12 c0, Current Cache Size Identification Register18 Instruction Set Attributes Register 4 bit functions 4KB 8KB 13 c0, Current Cache Level ID Register 3130 Reserved 14 c0, Cache Size Selection Register 15 c1, System Control Register 23 System Control Register bit functions AFETRE Nmfi Enables L1 data cache = data caching disabled. This is the reset value= data caching enabled = strict alignment fault checking enabled Auxiliary Control Registers C1, Auxiliary Control Register24 Auxiliary Control Register bit functions Axiscen AxiscuenDilsm Deolp Rsdis DbwrDlfo Dnch C15, Secondary Auxiliary Control Register 25 Secondary Auxiliary Control Register bit functions Doofmacs IXCOFC UFC 17 c1, Coprocessor Access Register Primary input RMWENRAM1 defines the reset valuePrimary input RMWENRAM0 defines the reset value Atcmecc Fault Status and Address Registers C5, Data Fault Status RegisterAll other encodings for these FSR bits are Reserved C5, Instruction Fault Status Register 28 Data Fault Status Register bit functionsTo use the Dfsr read or write CP15 with To access the Ifsr read or write CP15 with C5, Auxiliary Fault Status RegistersThere are two auxiliary fault status registers 29 Instruction Fault Status Register bit functions C6, Data Fault Address Register 30 Adfsr and Aifsr bit functions= Atcm = Btcm C6, Instruction Fault Address Register 19 c6, MPU memory region programming registers C6, MPU Region Size and Enable Registers C6, MPU Region Base Address Registers C6, MPU Region Access Control Registers 158 Sub-region disable32 Region Size Register bit functions 33 MPU Region Access Control Register bit functions TEX 34 Access data permission bit encoding C6, MPU Memory Region Number RegisterUNP 35 MPU Memory Region Number Register bit functions Cache operations Point of Coherency PoCPoint of Unification PoU Invalidate and clean operations Set and Way format 37shows the cache sizes and the resultant bit range for Set Address format36 Functional bits of c7 for Set and Way 37 Widths of the set field for L1 cache sizes Size Set Data Synchronization Barrier operation Data Memory Barrier operation21 c9, Btcm Region Register 38 Functional bits of c7 for address format Bits Field To access the Btcm Region Register, read or write CP15 with 22 c9, Atcm Region Register39 Btcm Region Register bit functions To access the Atcm Region Register, read or write CP15 with 23 c9, TCM Selection Register24 c11, Slave Port Control Register 40 Atcm Region Register bit functions 25 c13, Fcse PID Register 26 c13, Context ID Register312 Reserved RAZ/UNP 27 c13, Thread and Process ID Registers C15, nVAL IRQ Enable Set Register Validation RegistersCcnt overflow IRQ request C15, nVAL FIQ Enable Set Register Ccnt overflow FIQ request C15, nVAL Reset Enable Set Register C15, nVAL Debug Request Enable Set RegisterCcnt overflow reset request C15, nVAL IRQ Enable Clear Register Ccnt overflow debug request C15, nVAL FIQ Enable Clear Register 48 nVAL IRQ Enable Clear Register format C15, nVAL Reset Enable Clear Register 303 Reserved UNP or Sbzp C15, nVAL Debug Request Enable Clear Register 51 nVAL Debug Request Enable Clear Register format C15, nVAL Cache Size Override Register 50 nVAL Cache Size Override Register318 Reserved B0000 4kB B0001 8kB B0011 16kB B0111 32kB B1111 64kB Correctable Fault Location Register 53 Correctable Fault Location Register cache 52 Correctable Fault Location Register cache To access the Build Options 1 Register, write CP15 with Build Options RegistersC15, Build Options 1 Register C15, Build Options 2 Register 55 Build Options 2 Register NoicacheNodcache Atcmes Btcmes NoieNofpu Nompu To access the Build Options 2 Register, write CP15 with NoharderrorcachDcachees Axibusparity Prefetch Unit About the prefetch unit Branch prediction Disabling program flow prediction Configuring the branch predictor Branch predictorIncorrect predictions and correction Return stack Events and Performance Monitor Bit position Update Value About the eventsEvent bus interface bit functions Event ETMEXTOUT0 ETMEXTOUT1 Non-cacheable access on AXI master bus Instruction cache accessBut with different attributes Dual issue case a branch Dual issue case B1, B2, F2 load/store, F2D TCM correctable ECC error reported by load/store unit Yes TCM correctable ECC error reported by prefetch unit Yes About the PMU Performance monitoring registers Performance monitoring registers are described1 c9, Performance Monitor Control Register 2shows how the bit values correspond with the Pmnc Register 2 c9, Count Enable Set Register Pmnc Register bit functions To access the Cntens Register, read or write CP15 with 3 c9, Count Enable Clear RegisterCntens Register bit functions Bits Field Function To access the Cntenc Register, read or write CP15 with Cycle counter enable clear4 c9, Overflow Flag Status Register Cntenc Register bit functions Bits Field Function To access the Flag Register, read or write CP15 with 5shows how the bit values correspond with the Flag Register5 c9, Software Increment Register To access the Swincr Register, read or write CP15 with 6 c9, Performance Counter Selection RegisterSwincr Register bit functions Bits Field Function 313 Reserved RAZ on reads, Sbzp on writes Increment Counter 7 c9, Cycle Count Register 8 c9, Event Selection RegisterSEL To access the EVTSELx Register, read or write CP15 with EVTSELx Register bit functions 10 c9, User Enable Register 9 c9, Performance Monitor Count RegistersUseren Register bit functions 11 c9, Interrupt Enable Set Register Ccnt overflow interrupt enable10 Intens Register bit functions Bits Field Function 12 c9, Interrupt Enable Clear Register Ccnt overflow interrupt enable bit11 Intenc Register bit functions Bits Field Function To access the Intenc Register, read or write CP15 with Event bus interface Use of the event bus and counters MPU faults on MPU software-accessible registers onMemory Protection Unit Default memory map About the MPUTrue Memory regions Region base addressRegion size Subregions Region access permissions Region attributesOverlapping regions Region Example of using regions that overlap Example of using subregions Background regions TCM regions Using memory types Memory types ARM DDI 0363E Region attributes TEX20, C, and B encodings Description Memory Type Shareable? Cacheable memory policies 1BB On page 7-2shows the default memory map MPU interaction with memory systemFollowing code is an example of disabling the MPU MPU faults Background fault Permission fault Alignment faultBackground fault Permission fault MPU software-accessible registers On page 4-5shows the CP15 registers that control the MPU Level One Memory System About the L1 memory system L1 memory system block diagram About the error detection and correction schemes Parity Bit ECC onParity Error checking and correction Hard errorsBit ECC Read-Modify-Write Error correction Correct inlineCorrect-and-retry Fault handling FaultsClasses of fault that can occur are MPU faults External faults Cache and TCM parity and ECC errorsTCM external faults Fault status information Debug eventsPrecise and imprecise aborts Abort exceptions Precise abort exceptions Imprecise abort exceptionsUsage models Correctable errors Types of aborts Conditions Source Precise FatalAXI ARM DDI 0363E About the TCMs TCM attributes and permissions Atcm and Btcm configuration TCM internal error detection and correctionHandling TCM parity errors on Handling TCM ECC errors on Handling TCM parity errors Handling TCM ECC errorsTCM arbitration External TCM errors TCM initializationTCM port protocol AXI slave interfaces for TCMs About the caches Store buffer Cache maintenance operations Store buffer mergingStore buffer behavior Store buffer draining Cache error detection and correction Error build options Address decoder faults Handling cache parity errorsCache parity error behavior Value Behavior Handling cache ECC errors Cache ECC error behavior Value Behavior Errors on instruction cache read Errors on data cache readErrors on data cache write Errors on evictions Invalidate all instruction cache Clean data cache by set/way Cache RAM organization Tag RAMDirty RAM on Data RAM on Tag RAM Dirty RAM Data RAMCache sizes and tag RAM organization Tag RAM organization Organization of a dirty RAM line Nonsequential read operation performed with one RAM access Data RAM sizes without parity or ECC implemented 13 Data cache RAM bits, with parity Description Cache interaction with memory system Disabling or enabling all of the cachesFollowing code is an example of enabling caches 15 Data cache data RAM sizes with ECC Cache size Data RAMs Disabling or enabling error checking Disabling or enabling instruction cacheDisabling or enabling data cache MCR p15 R0, c1 Write System Control Register Internal exclusive monitor Memory types and L1 memory system behavior Error detection events TCM error eventsInstruction-cache error events Data-cache error events ARM DDI 0363E Level Two Interface About the L2 interface AXI master interface 1shows the AXI master interface attributesAttribute Value Comments Identifiers for AXI bus accesses Outstanding write/read access on different IDsOutstanding write accesses with the same ID Write response Eviction buffer Memory attributesArcachem and Awcachem encodings Encoding a Meaning Aruserm and Awuserm encodings Memory system implications for AXI accesses AXI master interface transfers Strongly Ordered and Device transactions onLinefills on Restrictions on AXI transfers Strongly Ordered and Device transactionsNon-cacheable Ldrb Address20 LDR or LDM that transfers one register Ldrh from Strongly Ordered or Device memory Address30 LDM that transfers five registers LDM5, Strongly Ordered or Device memory Address40 Strb to Strongly Ordered or Device memory Address40 Strh to Strongly Ordered or Device memory Address20 STR or STM of one register STM of seven registersFirst Wstrbm Linefills Cache line write-back evictionNon-cacheable reads 14 Ldrh from Non-cacheable Normal memory Address20 15 LDR or LDM1 from Non-cacheable Normal memory Address20 Non-cacheable or write-through writes AXI transaction splitting Normal write merging 20 AXI transaction splitting, data in two cache lines Example 9-1 Write merging ARM DDI 0363E AXI slave interface AXI slave interface for cache RAMs TCM parity and ECC support Cache parity and ECC supportAXI slave control AXI slave characteristics 25 AXI slave interface attributes Enabling or disabling AXI slave accesses Accessing RAMs using the AXI slave interface TCM RAM access on Cache RAM access on26 RAM region decode AxUSERS bit One-hot RAM select TCM RAM access ARADDRSMSB, see Table27 TCM chip-select decode Btcm ports RAM selected Cache RAM access Memory map when accessing the cache RAMsThis section contains the following Data RAM access 0010 Bank 0100 100031 Cache data RAM bank/address decode Inputs ARADDRS1815 0001 Bank 0010 0100 1000 34 Data format, instruction cache, with ECC 35 Data format, data cache, with ECC Data bit Description Tag RAM access ARM DDI 0363E Dirty RAM access 43 Dirty register format, with ECC Data bit Description Other examples of accessing cache RAMs ARADDRS1815 = 4b1111 Power Control About power control on Power management on About power control Run mode Standby modeDormant mode Shutdown mode Communication to the Power Management Controller Debug Debug state on Cache debug on Debug systems Debug host Protocol converter Debug targetDebug host Protocol converter About the debug unit Halting debug-mode debuggingMonitor debug-mode debugging Programming the debug unit All other state information associated with the debug unit 11.3.2 CP14 access permissions Debug register interfaceCoprocessor registers Coprocessor registers summary Offset Register Access Mnemonic Description Hex Number Memory-mapped registersInstruction Mnemonic Description Debug memory-mapped registers Memory addresses for breakpoints and watchpoints Power domains Effects of resets on debug registersAPB port access permissions Privilege of memory access permission External debug interface access permissions Registers LockOther Debug registers Other registers Accessing debug registers Debug register descriptions6shows the CP14 debug register map 11.4.2 CP14 c0, Debug ID Register Debug ID Register functions WRPBRP To use the Debug ID Register, read CP14 c0 with 11.4.3 CP14 c0, Debug ROM Address RegisterTo use the Debug ROM Address Register, read CP14 c0 with 11.4.4 CP14 c0, Debug Self Address Offset Register Debug Self Address Offset Register format Debug Self Address Offset Register functions 11.4.5 CP14 c1, Debug Status and Control Register 10 Debug Status and Control Register functions Flag is set to 1 on entry to debug state Execute ARM instruction enable bit = disabled, this is the reset valueARM DTR access mode MOE Data Transfer Register Watchpoint Fault Address Register 12 Watchpoint Fault Address Register functionsVector Catch Register Reserved RAZ SVC Bits Field Reset Description Value Debug State Cache Control RegisterInstruction Transfer Register 14 Debug State Cache Control Register functions Debug Run Control Register 15 Debug Run Control Register functions315 Reserved Breakpoint Value Registers Breakpoint Control Registers 17 Breakpoint Control Registers functions +0 is accessed Corresponding instruction address breakpoint18 Meaning of BVR bits BVR2220 Meaning Watchpoint Value Registers Watchpoint Control Registers19 Watchpoint Value Registers functions Bits Description 11 Watchpoint Control Registers format 20 Watchpoint Control Registers functions Accessed Operating System Lock Status Register Authentication Status Register 21 OS Lock Status Register functions Device Power-down and Reset Control Register Device Power-down and Reset Status Register= Dbgnopwrdwn is LOW. This is the reset value 23 Prcr functions 15 Prsr format 24 Prsr functions Management registers Processor ID Registers Claim Registers Claim Tag Set Register27 Claim Tag Set Register functions Bits Field Function Lock Access Register 318 Reserved RAZ or Sbzp Claim tag clear Reset value isClaim Tag Clear Register Lock Status Register Device Type Register Debug Identification Registers30 Device Type Register functions 32 Fields in the Peripheral Identification Registers Field Size Description33 Peripheral ID Register 0 functions Bits Value Description 34 Peripheral ID Register 1 functions 35 Peripheral ID Register 2 functions36 Peripheral ID Register 3 functions 37 Peripheral ID Register 4 functions 1020 Component Identification Register1021 1022 Debug events Software debug event Halting debug event Behavior of the processor on debug eventsDebug event priority Watchpoint debug events Debug exception 40shows the values in the link register after exceptions Following sections describeEffect of debug exceptions on CP15 registers and Wfar Four CP15 registers that record abort information are Avoiding unrecoverable states Debug state Privilege onEntering debug state 41 Read PC value after debug state entry Behavior of the PC and Cpsr in debug state 41 Read PC value after debug state entry Debug event Accessing registers and memory Executing instructions in debug stateWriting to the Cpsr in debug state Privilege Coprocessor instructions Effect of debug state on non-invasive debugEffects of debug events on processor registers Exceptions in debug state Precise Data abort Imprecise Data AbortImprecise Data Aborts on entry and exit from debug state Leaving debug state Sets the DSCR1 core restarted flag to Cache debug This section describes cache debug. It consistsCache pollution in debug state Cache coherency in debug state APB signals Miscellaneous debug signalsThis section describes the miscellaneous debug signals External debug interface Authentication signals Changing the authentication signals42 Authentication signal restrictions Dbgen a Non-invasive debug permitted Issue an Instruction Synchronization Barrier ISB instruction Using the debug functionality Example 11-1 Executing an ARM instruction through the ITR Rules for accessing the DCC Debug communications channel Software access to the DCC Debugger access to the DCCExample 11-5shows the code for host-to-target data transfer Example 11-4 Target to host data transfer host end Programming breakpoints and watchpoints This section describes the following operationsProgramming simple breakpoints and the byte address select Example 11-6 Polling the DCC host end Setting a simple aligned watchpoint Example 11-7 Setting a simple breakpoint Setting a simple unaligned watchpoint Example 11-8 Setting a simple aligned watchpoint Example 11-9 Setting a simple unaligned watchpoint 45shows some examplesSingle-stepping Not required Debug state entry Example 11-10 Single-stepping off an instructionExample 11-11 Entering debug state Debug state exit Example 11-12 Leaving debug state Accessing registers and memory in debug state This section describes the followingReading and writing registers through the DCC Example 11-13 Reading an ARM register Reading the PC in debug state Example 11-15shows the code to read the PCReading the Cpsr in debug state Example 11-16shows the code for reading the Cpsr Example 11-19 Checking for an abort after memory access Reading memoryExample 11-18shows the code for reading a byte of memory Example 11-17 Writing the Cpsr Example 11-20 Reading a block of bytes of memory Example 11-21 Reading a word of memory Example 11-22 Changing the DTR access mode Example 11-23 Reading registers in stall modeExample 11-24 Writing registers in stall mode Fast register read/write Fast memory read/write Example 11-25 Reading a block of words of memory Accessing coprocessor registers Example 11-27 Reading a coprocessor register 11-70 Emulating power down Debugging systems with energy management capabilities 11-72 FPU Programmer’s Model About the FPU programmer’s model FPU functionalityAbout the VFPv3-D16 architecture General-purpose registers FPU views of the register bank System registers VFPv3 architecture describes the following system registers1shows the VFP system registers in the Cortex-R4F FPU All hardware ID information is privileged access only Fpsid is privileged access onlyMvfr registers are privileged access only This is a change in VFPv3 compared to VFPv2 Floating-Point Status and Control Register, Fpscr Fpscr Register bit functionsDNM Rmode Floating-Point Exception Register, Fpexc LENIDE RAZ DNM IXE RAZ UFE OFE DZE IOE IDC Media and VFP Feature Registers, MVFR0 and MVFR1 Floating-Point Exception Register bit functionsDEX MVFR0 Register bit functions MVFR1 Register bit functions Full denormal arithmetic supported for VFP Full-compliance mode Flush-to-zero mode Default NaN mode Full-compliance modeFlush-to-zero mode Default NaN mode Compliance with the Ieee 754 standard Complete implementation of the Ieee 754 standardIeee 754 standard implementation choices NaN handling Comparisons UnderflowQNaN and SNaN handling CDP Exceptions Integration Test Registers About Integration Test Registers Software access using APB Programming and reading Integration Test Registers Register Itctrl ItetmifItmiscout Itmiscin Processor integration testing 13121110 Using the Integration Test Registers Performing integration testing Itetmif Register ETM interface Itetmif Register bit assignments Bits Name Function Itmiscout Register Miscellaneous Outputs Itmiscin Register Miscellaneous InputsItmiscout Register bit assignments Bits Name Function Integration Mode Control Register Itctrl Bits Name FunctionDbgrestart Etmextout Bits Access Reset value Name Function 7shows the fields of the Itctrl RegisterRAZ/SBZP Intmode Cycle Timings and Interlock Behavior Multiplies on Divide on Branches on Dual issue on About cycle timings and interlock behavior Instruction execution overview Following sequence where R1 is a Late Reg takes two cycles Flag-setting instructionsConditional instructions Definition of terms Assembler language syntax Register interlock examples Instruction Behavior SequenceTakes two cycles because there are no register dependencies Takes three cycles because of the result latency of R1 Data processing instructions Cycle counts if destination is not PCCycle counts if destination is the PC Example interlocks ShifterRegister controlled shifts QADD, QDADD, QSUB, and Qdsub instructions Media data-processing SEL Sum of Absolute Differences SAD Instruction sequence BehaviorResult of the USAD8 instruction USAD8 instruction Multiplies Umlals 14-13 Divide Branches 10 Branch instruction cycle timing behaviorExample instruction Cycles Memory Comments Mode changing Processor state updating instructionsAll MRS instructions All MSR instructions to the Spsr Single load and store instructions 13shows the cycle timing behavior for loads to the PC Base register update 13 Cycle timing behavior for loads to the PCExample instruction Cycles Memory Result Comments Latency 14-19 Register offset, then 3-issue cycles Load and Store Double instructions Load and Store Multiple instructions Write-back Load Multiples, where the PC is in the register list Correct condition prediction and correctReturn stack prediction Correct condition prediction and incorrect 14-23 RFE and SRS instructions Synchronization instructions Clrex Coprocessor instructions Some instructions such as cache operations take more cycles SVC formerly SWI Prefetch Abort Undefined Instruction Miscellaneous instructions Floating-point register transfer instructions Blocking and serializingSerializing Floating-point load/store instructions Bit aligned addressNot aligned 2,2 2,3 4,5 Floating-point single-precision data processing instructions Floating-point double-precision data processing instructions Dual issue Dual issue rules Permitted combinations onDual issue rules Dual issue First instruction Second instruction Case Permitted combinations28 Permitted instruction combinations Case F2stb Any single-precision CDPi, excludingMultiply-accumulate instructionso Case F2Db AC Characteristics Processor timing on Processor timing parameters on Processor timing Processor timing parameters Input port timing parametersClock uncertainty 10% Clock uncertainty 50% 3shows the timing parameters for the interrupt input ports 4shows the input timing parameters for the AXI master portClock uncertainty 60% 5shows the input timing parameters for the AXI slave port Rreadys 6shows the input timing parameters for the debug input ports 7shows the input timing parameters for the ETM input ports 8shows the timing parameters for the test input ports Clock uncertainty 65%Clock uncertainty 40% Output ports timing parameters 11shows the timing parameters for the interrupt output ports 13shows the timing parameters for the AXI slave output ports Write response channel Clock uncertainty 60% BRESPS10 16shows the timing parameters for the test output ports Clock uncertainty 45% 18shows the timing parameters for the FPU output signals Fpidc 15-13 Processor Signal Descriptions FPU signals on page A-23 About the processor signal descriptions AnyFrom any clock Global signals Table A-1 Global signalsSignal Direction Clocking Description Configuration signals Table A-2shows the processor configuration signalsTable A-2 Configuration signals Information Tie LOW for even parity Tie High for odd parity RMWENRAM10b Interrupt signals, including VIC interface signals L2 interface signals Table A-4 AXI master port signals for the L2 interfaceAXI master port Identification tag for the write data group of signals Identification tag for the write response signalIdentification tag for the read address group of signals Protection signals provide addition information about a bus AXI master port error detection signals Table A-5 AXI master port error detection signalsTable A-6 AXI slave port signals for the L2 interface AXI slave port Protection information, privileged/normal access. AWPROT0 AXI specificationProtection information, privileged/normal access. ARPROT0 One to 16. a four bit binary value minus one determines AXI slave port error detection signals ATCM, one hot. AWUSERS30 signal is not partStandard AXI specification Table A-7 AXI slave port error detection signals TCM interface signals Table A-8shows the Atcm port signalsTable A-9shows the B0TCM port signals Table A-10shows the B1TCM port signals Table A-10 B1TCM port signals= DMA B1TCM RAM access is sequential Address for B1TCM data RAMWrite data for B1TCM data RAM Write parity or ECC code for B1TCM Dual core interface signals Table A-11shows the dual redundant core interface signalsTable A-11 Dual core interface signals Debug interface signals Table A-13shows the debug miscellaneous signalsTable A-12 Debug interface signals Table A-13 Debug miscellaneous signals Input Tie-off Debug ROM physical address validInput Tie-off Debug self-address offset Input Tie-off Debug self-address offset valid ETM interface signals Table A-14shows the ETM interface signalsTable A-14 ETM interface signals Test signals Table A-15shows the test signalsTable A-15 Test signals Mbist signals Table A-16shows the Mbist signals Validation signals Table A-17shows the validation signals FPU signals Table A-18 FPU signals ECC Schemes ECC scheme selection guidelines on page B-2 ECC scheme selection guidelines NCPUHALT removed from timing diagram Added sections RevisionsClarified byte-invariant big-endian format Clarified little-endian format Table C-1 Differences between issue B and issue C Change Location Table C-2 Differences between issue C and issue D No technical changes Glossary Abort, and an internal or External AbortSee also Data Abort, External Abort and Prefetch Abort Base register write-back See also Advanced High-performance Bus See Advanced High-performance BusThat are divisible by four and two respectively See Advanced Microcontroller Bus Architecture Active read transaction Active transferActive write transaction Completed transfer Read ID width Read issuing capabilityWrite ID capability Write ID width See also Burst See also Beat Accesses are expected to be word-aligned Accessed in parallel during a cache look-upSee also Word-invariant Bus See also Dirty See also Clean See Embedded Trace Macrocell An instruction that is architecturally Undefined By individual implementationsOption chosen does not affect software compatibility Precision and the fraction is all zeros Serviced while normal program execution is suspended See also Halt modeSee Cold reset Result of attempting to access invalid instruction memory Or equal to 1 and is not restricted to being a power of two See Should Be OneSee Should Be Zero See Boundary scan chain See Debug test access port Increment of +2Destination precision User trap handler is executed Expected behavior for an unaligned access Bit for the exception is setProcessor-specific. a victim is also known as a cast out A processor Cache terminology diagram