ARM r1p3, R4F See Processor, See Cache miss, Serviced while normal program execution is suspended

	Glossary
Load Store Unit (LSU)	The part of a processor that handles load and store transfers.
LSU	See Load Store Unit.
Macrocell	A complex logic block with a defined interface and behavior. A typical VLSI system comprises
	several macrocells (such as a processor, an ETM, and a memory block) plus application-specific
	logic.
Memory coherency	A memory is coherent if the value read by a data read or instruction fetch is the value that was
	most recently written to that location. Memory coherency is made difficult when there are
	multiple possible physical locations that are involved, such as a system that has main memory,
	a write buffer and a cache.

Memory Protection Unit (MPU)

Hardware that controls access permissions to blocks of memory. Unlike an MMU, an MPU does not translate virtual addresses to physical addresses.

Microprocessor	See Processor.
Miss	See Cache miss.
Monitor debug-mode	One of two mutually exclusive debug modes. In Monitor debug-mode the processor enables a
	software abort handler provided by the debug monitor or operating system debug task. When a
	breakpoint or watchpoint is encountered, this enables vital system interrupts to continue to be
	serviced while normal program execution is suspended.
	See also Halt mode.
MPU	See Memory Protection Unit.
NaN	Not a number. A symbolic entity encoded in a floating-point format that has the maximum
	exponent field and a nonzero fraction. An SNaN causes an invalid operand exception if used as
	an operand and a most significant fraction bit of zero. A QNaN propagates through almost every
	arithmetic operation without signaling exceptions and has a most significant fraction bit of one.
Penalty	The number of cycles in which no useful Execute stage pipeline activity can occur because the
	instruction flow is different from that assumed or predicted.
Power-on reset	See Cold reset.
Prefetching	In pipelined processors, the process of fetching instructions from memory to fill up the pipeline
	before the preceding instructions have finished executing. Prefetching an instruction does not
	mean that the instruction has to be executed.
Prefetch Abort	An indication from a memory system to the processor that an instruction has been fetched from
	an illegal memory location. An exception must be taken if the processor attempts to execute the
	instruction. A Prefetch Abort can be caused by the external or internal memory system as a
	result of attempting to access invalid instruction memory.
	See also Data Abort, External Abort and Abort.
Processor	A contraction of microprocessor. A processor includes the CPU or core, plus additional
	components such as memory, and interfaces. These are combined as a single macrocell, that can
	be fabricated on an integrated circuit.
Read	Reads are defined as memory operations that have the semantics of a load. That is, the ARM
	instructions LDM, LDRD, LDC, LDR, LDRT, LDRSH, LDRH, LDRSB, LDRB, LDRBT, LDREX, RFE, STREX, SWP, and
	SWPB, and the Thumb instructions LDM, LDR, LDRSH, LDRH, LDRSB, LDRB, and POP.
Region	A partition of instruction or data memory space.

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