ARM R4F Active read transaction, Active transfer, Active write transaction, Completed transfer

Glossary

•the master and slave interface conventions for AXI components.

AXI

master

Write address channel (AW) Write data channel (W)

Write response channel (B) Read address channel (AR)

Read data channel (R)

AXI

interconnect

Write address channel (AW) Write data channel (W)

Write response channel (B) Read address channel (AR)

Read data channel (R)

AXI

slave

AXI master	AXI slave	AXI master	AXI slave
interface	interface	interface	interface
AXI terminology	The following AXI terms are general. They apply to both masters and slaves:

Active read transaction

A transaction for which the read address has transferred, but the last read data has not yet transferred.

Active transfer

A transfer for which the xVALID1 handshake has asserted, but for which xREADY has not yet asserted.

Active write transaction

A transaction for which the write address and/or leading write data has transferred, but the write response has not yet transferred.

Completed transfer

A transfer for which the xVALID/xREADY handshake is complete.

Payload The non-handshake signals in a transfer.

Transaction An entire burst of transfers, comprising an address, one or more data transfers and a response transfer (writes only).

Transmit An initiator driving the payload and asserting the relevant xVALID signal.

Transfer A single exchange of information. That is, with one xVALID/xREADY handshake.

The following AXI terms are master interface attributes. To obtain optimum performance, they must be specified for all components with an AXI master interface:

Combined issuing capability

The maximum number of active transactions that a master interface can generate. This is specified instead of write or read issuing capability for master interfaces that use a combined storage for active write and read transactions.

Read ID capability

The maximum number of different ARID values that a master interface can generate for all active read transactions at any one time.

1.The letter x in the signal name denotes an AXI channel as follows:

AW Write address channel.

WWrite data channel.

BWrite response channel.

AR Read address channel.

RRead data channel.

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