Programmer’s Model

2.8Exceptions

Exceptions are taken whenever the normal flow of a program must temporarily halt, for example, to service an interrupt from a peripheral. Before attempting to handle an exception, the processor preserves the critical parts of the current processor state so that the original program can resume when the handler routine has finished.

This section provides information of the processor exception handling:

Exception entry and exit summary

Reset on page 2-18

Interrupts on page 2-18

Aborts on page 2-22

Supervisor call instruction on page 2-24

Undefined instruction on page 2-25

Breakpoint instruction on page 2-25

Exception vectors on page 2-26.

Note

When the processor is in debug halt state, and an exception occurs, it is handled differently to normal. See Exceptions in debug state on page 11-47for more details

2.8.1Exception entry and exit summary

Table 2-4summarizes the PC value preserved in the relevant R14 on exception entry, and the recommended instruction for exiting the exception handler.

 

 

 

Table 2-4 Exception entry and exit

 

 

 

 

Exception

Recommended return instruction

Previous state

Notes

 

 

or entry

ARM R14_x

Thumb R14_x

 

 

 

 

 

 

 

 

 

 

SVCa

MOVS PC, R14_svc

IA + 4

IA + 2

Where the IA is the

 

 

 

 

address of the SVC or

UNDEF

Variesb

IA + 4

IA + 2

Undefined instruction.

PABT

SUBS PC, R14_abt, #4

IA + 4

IA + 4

Where the IA is the

 

 

 

 

address of instruction that

 

 

 

 

had the Prefetch Abort.

FIQ

SUBS

PC,

R14_fiq,

#4

IA + 4

IA + 4

 

 

 

 

 

 

 

IRQ

SUBS

PC,

R14_irq,

#4

IA + 4

IA + 4

Where the IA is the address of the instruction that was not executed because the FIQ or IRQ took priority.

DABT

SUBS PC, R14_abt, #8

IA + 8

IA + 8

Where the IA is the

 

 

 

 

address of the Load or

 

 

 

 

Store instruction that

 

 

 

 

generated the Data Abort.

 

 

 

 

 

RESET

NA

-

-

The value saved in

 

 

 

 

R14_svc on reset is

 

 

 

 

Unpredictable.

 

 

 

 

 

BKPT

SUBS PC, R14_abt, #4

IA + 4

IA + 4

Software breakpoint.

a.

Formerly SWI.

 

 

 

 

ARM DDI 0363E

Copyright © 2009 ARM Limited. All rights reserved.

2-16

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ARM r1p3, R4F manual Exceptions, Exception entry and exit summary, Reset on Interrupts on Aborts on