Invalidate and clean operations, Set and Way format

System Control Coprocessor

CRn	Opcode_1	CRm	Opcode_2
c7	0	c0	4	SBZ
		c5	0	SBZ
			1	MVA
			4	SBZ
			6	SBZ
			7
		c6	1	MVA
			2	Way
		c10	1	MVA
			2	Way
			4	SBZ
			5	SBZ
		c11	1	MVA
		c14	1	MVA
			2	Way
c15	0	c5	0	SBZ

Wait For Interrupt (NOP) Invalidate All Instruction Caches

Invalidate Instruction Cache Line to Point-of-Unification by MVA

Flush Prefetch buffer

Invalidate entire branch predictor array (NOP) Invalidate VA from Branch Predictor Array (NOP) Invalidate data cache line to Point-of-Coherency by MVA Invalidate data cache line by set/way

Clean data cache line to Point-of-Coherency by MVA Clean data cache line by set/way

Data Synchronization Barrier

Data Memory Barrier

Clean data cache line to Point-of-Unification by MVA

Clean and Invalidate data cache line to Point-of-Unification by MVA Clean and Invalidate data cache line by set/way

Invalidate all Data Caches

Read-only

Read/write

SBZ

MVA

Way

Write-only	Accessible in User mode
Should Be Zero
Using MVA
Using Set and Way

Figure 4-38 Cache operations

In addition to the register c7 cache management functions in this processor, an Invalidate all data caches operation is provided as a c15 operation. For convenience, that c15 operation is also described in this section.

Note

•Writing c7 with a combination of CRm and Opcode_2 not listed in Figure 4-38results in an Undefined exception.

•In this processor, reading from c7 causes an Undefined exception.

•All accesses to c7 can only be executed in a Privileged mode of operation, except for the Flush Prefetch Buffer, Data Synchronization Barrier, and Data Memory Barrier operations. These can be performed in User mode. Attempting to execute a Privileged instruction in User mode results in an Undefined exception.

•This processor does not contain an address-based branch predictor array.