ARM r1p3, R4, R4F

Programmer’s Model

ID013010 Non-Confidential, Unrestricted Access

• perform the appropriate data transfers on behalf of the aborted instruction and return to

the instruction after the abandoned instruction

• treat the error as fatal and terminate the process.

If the abort handler returns to the abandoned instruction, some of the memory accesses

generated are repeated. The effect is that multiword load/store instructions can access the same

memory location twice. The first access occurs before the abort is detected, and the second when

the instruction is restarted.

In Strongly Ordered or Device type memory, repeating memory accesses might have

unacceptable side-effects. Therefore, if the abort handler can fix the error and re-execute the

aborted instruction, you must ensure that for all memory errors on multiword load/store

instructions, either:

• all side effects of repeating accesses are inconsequential

• the error must either occur on the first word accessed or not at all.

The instructions that this rule applies to are:

• All forms of ARM instructions

LDM

, and

LDRD

, all forms of

STM

STRD

including VFP

variants, and unaligned

LDR

STR

LDRH

, and

STRH

• Thumb instructions

LDMIA

LDRD

SDRD

PUSH

POP

, and

STMIA

including VFP variants, and

unaligned

LDR

STR

LDRH

, and

STRH

Abort handler

If you configure the processor with parity or ECC on the caches or the TCMs, and the abort

handler is in one of these memories, then it is possible for a parity or ECC error to occur in the

abort handler. If the error is not recoverable, then a precise abort occurs and the processor loops

until the next interrupt. The LR and SPSR values for the original abort are also lost. Therefore,

you must construct software that ensures that no precise aborts occur when in the abort handler.

This means the abort handler must be in external memory and not cached.

2.8.5 Supervisor call instruction

You can use the SuperVisor Call (SVC) instruction (formerly SWI) to enter Supervisor mode,

usually to request a particular supervisor function. The SVC handler reads the opcode to extract

the SVC function number. A SVC handler returns by executing the following instruction,

irrespective of the processor operating state:

MOVS PC, R14_svc

This action restores the PC and CPSR, and returns to the instruction following the SVC.

IRQs are disabled when a software interrupt occurs.

The processor modifies the IT execution state bits on exception entry so that the values that the

processor writes into the SPSR are correct for the instruction following the SVC. This means

that the SVC handler does not have to perform any special action to accommodate the IT

instruction. For more information on the IT instruction, see the ARM Architecture Reference

Manual.