ARM r1p3, R4F Execution pipeline stages, Names of the pipeline stages and their functions are

Introduction

1.7Execution pipeline stages

The following stages make up the pipeline:

•the Fetch stages

•the Decode stages

•an Issue stage

•the three or four Execution stages.

Figure 1-2shows the Fetch and Decode pipeline stages of the processor and the pipeline operations that can take place at each stage.

Fe1 Fe2 Pd De

1st fetch

stage

2nd fetch

stage

Instruction formatting branch predicting

Instruction

decode

			Predicted branches and returns
		Figure 1-2 Processor Fetch and Decode pipeline stages
The names of the pipeline stages and their functions are:
Fe	Instruction fetch where data is returned from instruction memory.
Pd	Pre-decode where instructions are formatted and branch prediction occurs.
De	Instruction decode.

Figure 1-3shows the Issue and Execution pipeline stages for the Cortex-R4 processor.

Iss	Ex1
Register
	DC1
read,
address
generation,
and
instruction	EX1
issue

Ex2

DC2

EX1

Wr

Wr

Ret

Load/store

pipeline

Data

processing

pipeline

Mispredicted direct branches

Exception flush and mispredicted

indirect branches

Figure 1-3 Cortex-R4 Issue and Execution pipeline stages

Figure 1-4 on page 1-18shows the Issue and Execution pipeline stages for the Cortex-R4F processor.

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