ARM r1p3, R4, R4F

Cycle Timings and Interlock Behavior

ID013010 Non-Confidential, Unrestricted Access

Only cycle times for aligned accesses are given because Unaligned accesses to the PC are not

supported.

The processor includes a 4-entry return stack that can predict procedure returns. Any LDR

instruction to the PC with an immediate post-indexed offset of plus four, and the stack pointer

R13 as the base register is considered a procedure return.

Table14-14 shows the explanation of

<addr_md_1cycle>

and

<addr_md_3cycle>

used in

Table14-12 on page 14-17 and Table 14-13 on page 14-17.

14.11.1 Base register update

The base register update for load or store instructions occurs in the ALU pipeline. To prevent an

interlock for back-to-back load or store instructions reusing the same base register, there is a

local forwarding path to recycle the updated base register around the address generator. This

only applies when the load or store instruction with base write-back uses pre-increment

addressing, and is a single load or store instruction that is not a load or store double instruction

or load or store multiple instruction.

For example, with

aligned the following instruction sequence take three cycles to execute:

LDR R5, [R2, #4]!

LDR <cond> pc, [sp, #<imm>]

(!)

8 1 - Conditional predicted incorrectly, but return

stack predicted correctly

LDR <cond> pc, [sp], #cn

s8 1 -

LDR pc, <addr_md_1cycle>

a91 - -

LDR pc, <addr_md_3cycle>

11 1 - -

a. See Table14-14 for an explanation of

<addr_md_1cycle>

and

<addr_md_3cycle>

. For condition code failing cycle counts, you

must use the cycles for the non-PC destination variants.

Table14-13 Cycle timing behavior for loads to the PC (continued)

Example instruction Cycles Memory

cycles

Result

latency Comments

Table14-14 <addr_md_1cycle> and <addr_md_3cycle> LDR example instruction explanation

Example instruction Very Early Reg Comments

<addr_md_1cycle>

LDR <Rt>, [<Rn>, #<imm>] (!) <Rn>

If post-increment addressing or pre-increment

addressing with an immediate offset, or a

positive register offset with no shift or shift

LSL #1, 2 or 3, then 1-issue cycle

LDR <Rt>, [<Rn>, <Rm>] (!) <Rn>, <Rm>

LDR <Rt>, [<Rn>, <Rm>, LSL #1, 2 or 3] (!) <Rn>, <Rm>

LDR <Rt>, [<Rn>], #<imm> <Rn>

LDR <Rt>, [<Rn>], +/-<Rm> <Rn>, <Rm>

LDR <Rt>, [<Rn>], +/-<Rm> <shift> <cns> <Rn>, <Rm>

<addr_md_3cycle>

LDR <Rt>, [<Rn>, -<Rm>] (!) <Rn>,<Rm>

If pre-increment addressing with a negative

3, then 3-issue cycles

LDR <Rt>, [Rn, +/-<Rm> <shift> <cns>] (!) <Rn>,<Rm>