ARM R4F, r1p3 manual Clocking, AXI interface clocking Clock gating

Processor Initialization, Resets, and Clocking

3.4Clocking

The processor has two functional clock inputs. Externally to the processor, you must connect together CLKIN and FREECLKIN.

In addition, there is the PCLKDBG clock for the debug APB bus. This is asynchronous to the main clock.

All clocks can be stopped indefinitely without loss of state.

Three additional clock inputs, CLKIN2, DUALCLKIN, and DUALCLKIN2, are related to the dual-redundant core functionality, if included. If you are integrating a Cortex-R4 macrocell with dual-redundant core, contact the implementer of that macrocell for information about how to connect the clock inputs.

The following is described in this section:

•AXI interface clocking

•Clock gating.

3.4.1AXI interface clocking

The AXI master and AXI slave interfaces must be connected to AXI systems that are synchronous to the processor clock, CLKIN, even if this might be at a lower frequency. This means that every rising edge on the AXI system clock must be synchronous to a rising edge on

CLKIN.

The AXI master interface clock enable signal ACLKENM and the AXI slave interface clock enable signal ACLKENS must be asserted on every CLKIN rising edge for which there is a simultaneous rising edge on the AXI system clock.

Figure 3-2shows an example in which the processor is clocked at 400MHz (CLKIN), while the AXI system connected to the AXI master interface is clocked at 200MHz (ACLKM). The ACLKENM clock indicates the relationship between the two clocks.

CLKIN

ACLKM

ACLKENM

Figure 3-2 AXI interface clocking

If the AXI system connected to an interface is clocked at the same frequency as the processor, then the corresponding clock enable signal must be tied HIGH.

3.4.2Clock gating

You can use the STANDBYWFI output to gate the clock to the TCMs when the processor is in Standby mode. If you do, you must design the logic so that the TCM clock starts running within four cycles of STANDBYWFI going LOW.

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