Events and Performance Monitor

 

 

Table 6-1 Event bus interface bit functions (continued)

 

 

 

 

 

 

EVNTBUS

Description

CFLR

Event

 

Ref.

 

bit position

update

 

 

Value

 

 

 

 

 

 

 

 

 

[22]

Instruction cache tag RAM parity or ECC error (correctable).

Yes

0x4A

 

 

 

 

 

[23]

Instruction cache data RAM parity or ECC error (correctable).

Yes

0x4B

 

 

 

 

 

[24]

Data cache tag or dirty RAM parity error or correctable ECC error.

Yes

0x4C

 

 

 

 

 

[25]

Data cache data RAM parity error. or correctable ECC error

Yes

0x4D

 

 

 

 

 

[26]

TCM parity error or fatal ECC error reported from the prefetch unit.

-

0x4E

 

 

 

 

 

[27]

TCM parity error or fatal ECC error reported from the load/store unit.

-

0x4F

 

 

 

 

 

 

N/A

Store buffer merge.

-

0x50

 

 

 

 

 

 

N/A

LSU stall caused by full store buffer.

-

0x51

 

 

 

 

 

 

N/A

LSU stall caused by store queue full.

-

0x52

 

 

 

 

 

 

N/A

Integer divide instruction, SDIV or UDIV, executed.

-

0x53

 

 

 

 

 

 

N/A

Stall cycle caused by integer divide.

-

0x54

 

 

 

 

 

 

N/A

PLD instruction that initiates a linefill.

-

0x55

 

 

 

 

 

 

N/A

PLD instruction that did not initiate a linefill because of a resource shortage.

-

0x56

 

 

 

 

 

 

N/A

Non-cacheable access on AXI master bus.

-

0x57

 

 

 

 

 

[28]

Instruction cache access.

-

0x58

 

 

This is an analog to event 0x04.

 

 

 

 

 

 

 

 

N/A

Store buffer operation has detected that two slots have data in same cache line

-

0x59

 

 

but with different attributes.

 

 

 

 

 

 

 

[29]

Dual issue case A (branch).

-

0x5A

 

 

 

 

 

[30]

Dual issue case B1, B2, F2 (load/store), F2D.

-

0x5B

 

 

 

 

 

[31]

Dual issue other.

-

0x5C

 

 

 

 

 

[32]

Double precision floating point arithmetic or conversion instruction executed.

-

0x5D

 

 

 

 

 

[33]

Data cache data RAM fatal ECC error.

-

0x60

 

 

 

 

 

[34]

Data cache tag/dirty RAM fatal ECC error.

-

0x61

 

 

 

 

 

 

[35]

Processor livelock because of hard errors or exception at exception vector.a

-

0x62

[36]

Unused.

-

0x63

 

 

 

 

 

[37]

ATCM parity or multi-bit ECC error.

-

0x64

 

 

 

 

 

[38]

B0TCM parity or multi-bit ECC error.

-

0x65

 

 

 

 

 

[39]

B1TCM parity or multi-bit ECC error.

-

0x66

 

 

 

 

 

[40]

ATCM single-bit ECC error.

-

0x67

 

 

 

 

 

[41]

B0TCM single-bit ECC error.

-

0x68

 

 

 

 

 

[42]

B1TCM single-bit ECC error.

-

0x69

 

 

 

 

 

ARM DDI 0363E

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ARM R4F Store buffer merge, LSU stall caused by full store buffer, LSU stall caused by store queue full, Dual issue other