Processor Signal Descriptions

 

Table A-13 Debug miscellaneous signals (continued)

 

 

 

 

Name

Direction

Clocking

Description

 

 

 

 

DBGROMADDRV

Input

Tie-off

Debug ROM physical address valid

 

 

 

 

DBGSELFADDR[31:12]

Input

Tie-off

Debug self-address offset

 

 

 

 

DBGSELFADDRV

Input

Tie-off

Debug self-address offset valid

a. Not available in r0px revisions of the processor.

ARM DDI 0363E

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ARM r1p3, R4F manual Table A-13 Debug miscellaneous signals, Input Tie-off Debug ROM physical address valid