ARM r1p3, R4, R4F 7.3 Region attributes

Memory Protection Unit

ID013010 Non-Confidential, Unrestricted Access

7.3 Region attributes

Each region has a number of attributes associated with it. These control how a memory access

is performed when the processor accesses an address that falls within a given region. The

attributes are:

• Memory type, see Memory types on page7-7, one of:

— Strongly Ordered

—Device

— Normal

• Shared or Non-shared

• Non-cacheable

• Write-through cacheable

• Write-back cacheable

• Read allocation

• Write allocation.

The Region Access Control Registers use five bits to encode the memory region type. These are

the TEX)[2:0], C and B bits. Table7-3 shows the mapping of these bits to memory region

attributes.

Note

In earlier versions of the architecture, the TEX, C, and B bits were known as the Type Extension,

Cacheable and Bufferable bits. These names no longer adequately describe the function of the

B, C, and TEX bits.

All memory attributes which are Cacheable, write-back or write-through, are also implicitly

read-allocate. Table7-3 shows which attributes are write-allocate.

In addition, the Region Access Control Registers contain the shared bit, S. This bit only applies

to Normal memory, and determines whether the memory region is Shared (1) or Non-shared (0).

Table7-3 TEX[2:0], C, and B encodings

TEX[2:0] C B Description Memory Type Shareable?

000 0 0 Strongly-ordered. Strongly-ordered Shareable

000 0 1 Shareable Device. Device Shareable

000 1 0 Outer and Inner write-through, no write-allocate. Normal S bita

000 1 1 Outer and Inner write-back, no write-allocate. Normal S bita

001 0 0 Outer and Inner Non-cacheable. Normal S bita

001 0 1 Reserved. - -

001 1 0

001 1 1 Outer and Inner write-back, write-allocate. Normal S bita

010 0 0 Non-shareable Device. Device Non-shareable

010 0 1 Reserved. - -